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authorChris Johns <chrisj@rtems.org>2022-07-22 16:27:12 +1000
committerChris Johns <chrisj@rtems.org>2022-07-28 09:04:46 +1000
commit51ffa21011a8f62649af0c98d27a1717eaa1e96d (patch)
tree1e05bf98a9c88667c1ebe31a76832c7d688800c7 /bsps
parentbasp/aarch64: Make the unexpected sections origin address 64bit (diff)
downloadrtems-51ffa21011a8f62649af0c98d27a1717eaa1e96d.tar.bz2
aarch64/versal: Support DDRMC0 region 0 and 1
- Support DDRMC0 region 0 up to 2G in size - Support DDRMC0 region 1 with DDR memory greater than 2G up to the DDRMC0 max amount - Extend the heap with region 1's memory Closes #4684
Diffstat (limited to '')
-rw-r--r--bsps/aarch64/xilinx-versal/include/bsp.h9
-rw-r--r--bsps/aarch64/xilinx-versal/start/bspstartmmu.c49
-rw-r--r--bsps/include/bsp/fatal.h1
3 files changed, 59 insertions, 0 deletions
diff --git a/bsps/aarch64/xilinx-versal/include/bsp.h b/bsps/aarch64/xilinx-versal/include/bsp.h
index 2017e10ade..0bd93f28bc 100644
--- a/bsps/aarch64/xilinx-versal/include/bsp.h
+++ b/bsps/aarch64/xilinx-versal/include/bsp.h
@@ -47,6 +47,7 @@
#ifndef ASM
#include <bsp/default-initial-extension.h>
+#include <bsp/linker-symbols.h>
#include <bsp/start.h>
#include <rtems.h>
@@ -61,6 +62,14 @@ extern "C" {
#define BSP_RESET_SMC
+/*
+ * DDRMC mapping
+ */
+LINKER_SYMBOL(bsp_r0_ram_base)
+LINKER_SYMBOL(bsp_r0_ram_end)
+LINKER_SYMBOL(bsp_r1_ram_base)
+LINKER_SYMBOL(bsp_r1_ram_end)
+
/**
* @brief Versal specific set up of the MMU.
*
diff --git a/bsps/aarch64/xilinx-versal/start/bspstartmmu.c b/bsps/aarch64/xilinx-versal/start/bspstartmmu.c
index 5949111d0d..b2da3bc60d 100644
--- a/bsps/aarch64/xilinx-versal/start/bspstartmmu.c
+++ b/bsps/aarch64/xilinx-versal/start/bspstartmmu.c
@@ -38,6 +38,9 @@
#include <bsp/aarch64-mmu.h>
#include <libcpu/mmu-vmsav8-64.h>
+#include <rtems/malloc.h>
+#include <rtems/sysinit.h>
+
BSP_START_DATA_SECTION static const aarch64_mmu_config_entry
versal_mmu_config_table[] = {
AARCH64_MMU_DEFAULT_SECTIONS,
@@ -57,6 +60,29 @@ versal_mmu_config_table[] = {
.begin = 0xff000000U,
.end = 0xffc00000U,
.flags = AARCH64_MMU_DEVICE
+ }, { /* DDRMC0_region1_mem, if not used size is 0 and ignored */
+ .begin = (uintptr_t) bsp_r1_ram_base,
+ .end = (uintptr_t) bsp_r1_ram_end,
+ .flags = AARCH64_MMU_DATA_RW_CACHED
+ }
+};
+
+/*
+ * Create an MMU table to get the R1 base and end. This avoids
+ * relocation errors as the R1 addresses are in the upper A64 address
+ * space.
+ *
+ * The versal_mmu_config_table table cannot be used because the regions
+ * in that table have no identifiers to indicate which region is the
+ * the DDRMC0_region1_mem region.
+ */
+static const struct mem_region {
+ uintptr_t begin;
+ uintptr_t end;
+} bsp_r1_region[] = {
+ { /* DDRMC0_region1_mem, if not used size is 0 and ignored */
+ .begin = (uintptr_t) bsp_r1_ram_base,
+ .end = (uintptr_t) bsp_r1_ram_end,
}
};
@@ -78,3 +104,26 @@ versal_setup_mmu_and_cache( void )
aarch64_mmu_enable();
}
+
+void bsp_r1_heap_extend(void);
+void bsp_r1_heap_extend(void)
+{
+ const struct mem_region* r1 = &bsp_r1_region[0];
+ if (r1->begin != r1->end) {
+ rtems_status_code sc =
+ rtems_heap_extend((void*) r1->begin, r1->end - r1->begin);
+ if (sc != RTEMS_SUCCESSFUL) {
+ bsp_fatal(BSP_FATAL_HEAP_EXTEND_ERROR);
+ }
+ }
+}
+
+/*
+ * Initialise after the IDLE thread exists so the protected heap
+ * extend call has a valid context.
+ */
+RTEMS_SYSINIT_ITEM(
+ bsp_r1_heap_extend,
+ RTEMS_SYSINIT_IDLE_THREADS,
+ RTEMS_SYSINIT_ORDER_LAST
+);
diff --git a/bsps/include/bsp/fatal.h b/bsps/include/bsp/fatal.h
index e37e47d7ed..f350fe9f48 100644
--- a/bsps/include/bsp/fatal.h
+++ b/bsps/include/bsp/fatal.h
@@ -73,6 +73,7 @@ typedef enum {
BSP_FATAL_CONSOLE_INSTALL_1,
BSP_FATAL_CONSOLE_REGISTER_DEV_2,
BSP_FATAL_MMU_ADDRESS_INVALID,
+ BSP_FATAL_HEAP_EXTEND_ERROR,
/* ARM fatal codes */
BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(1),