bsps/irq: Add rtems_interrupt_raise()

Add rtems_interrupt_raise_on() and rtems_interrupt_clear().

Add a default implementation which just returns RTEMS_UNSATISFIED for
valid parameters.

Update #3269.

6 files changed, 144 insertions, 0 deletions

diff --git a/bsps/shared/dev/irq/arm-gicv2.c b/bsps/shared/dev/irq/arm-gicv2.c
index 045b7822a8..299ed5a089 100644
--- a/bsps/shared/dev/irq/arm-gicv2.c
+++ b/bsps/shared/dev/irq/arm-gicv2.c
@@ -64,6 +64,29 @@ void bsp_interrupt_dispatch(void)
   }
 }
 
+rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
+{
+  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+  return RTEMS_UNSATISFIED;
+}
+
+#if defined(RTEMS_SMP)
+rtems_status_code bsp_interrupt_raise_on(
+  rtems_vector_number vector,
+  uint32_t            cpu_index
+)
+{
+  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+  return RTEMS_UNSATISFIED;
+}
+#endif
+
+rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
+{
+  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+  return RTEMS_UNSATISFIED;
+}
+
 rtems_status_code bsp_interrupt_vector_is_enabled(
   rtems_vector_number vector,
   bool               *enabled
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index 0549b6bd72..82f3d3730d 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -164,6 +164,29 @@ void bsp_interrupt_dispatch(void)
   }
 }
 
+rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
+{
+  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+  return RTEMS_UNSATISFIED;
+}
+
+#if defined(RTEMS_SMP)
+rtems_status_code bsp_interrupt_raise_on(
+  rtems_vector_number vector,
+  uint32_t            cpu_index
+)
+{
+  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+  return RTEMS_UNSATISFIED;
+}
+#endif
+
+rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
+{
+  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+  return RTEMS_UNSATISFIED;
+}
+
 rtems_status_code bsp_interrupt_vector_is_enabled(
   rtems_vector_number vector,
   bool               *enabled
diff --git a/bsps/shared/irq-default-sources.am b/bsps/shared/irq-default-sources.am
index fe3352f7e5..41167ee2bc 100644
--- a/bsps/shared/irq-default-sources.am
+++ b/bsps/shared/irq-default-sources.am
@@ -1,4 +1,5 @@
 librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-affinity.c
+librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-raise-clear.c
 librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default.c
 librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c
 librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-enable-disable.c
diff --git a/bsps/shared/irq-sources.am b/bsps/shared/irq-sources.am
index d2536eb56d..97e1f05167 100644
--- a/bsps/shared/irq-sources.am
+++ b/bsps/shared/irq-sources.am
@@ -1,4 +1,5 @@
 librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-affinity.c
+librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-raise-clear.c
 librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-enable-disable.c
 librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-generic.c
 librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-handler-iterate.c
diff --git a/bsps/shared/irq/irq-default.c b/bsps/shared/irq/irq-default.c
index 842cdd66e0..63ba0c37ee 100644
--- a/bsps/shared/irq/irq-default.c
+++ b/bsps/shared/irq/irq-default.c
@@ -37,6 +37,18 @@
 
 #include <bsp/irq-generic.h>
 
+rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
+{
+  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+  return RTEMS_UNSATISFIED;
+}
+
+rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
+{
+  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+  return RTEMS_UNSATISFIED;
+}
+
 rtems_status_code bsp_interrupt_vector_is_enabled(
   rtems_vector_number vector,
   bool               *enabled
diff --git a/bsps/shared/irq/irq-raise-clear.c b/bsps/shared/irq/irq-raise-clear.c
new file mode 100644
index 0000000000..a0569f5948
--- /dev/null
+++ b/bsps/shared/irq/irq-raise-clear.c
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief This source file contains the implementation of
+ *   rtems_interrupt_raise(), rtems_interrupt_raise_on() and
+ *   rtems_interrupt_clear().
+ */
+
+/*
+ * Copyright (C) 2021 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp/irq-generic.h>
+
+#include <rtems/score/processormask.h>
+#include <rtems/score/smpimpl.h>
+#include <rtems/config.h>
+
+rtems_status_code rtems_interrupt_raise( rtems_vector_number vector )
+{
+  if ( !bsp_interrupt_is_valid_vector( vector ) ) {
+    return RTEMS_INVALID_ID;
+  }
+
+  return bsp_interrupt_raise( vector );
+}
+
+rtems_status_code rtems_interrupt_raise_on(
+  rtems_vector_number vector,
+  uint32_t            cpu_index
+)
+{
+  if ( !bsp_interrupt_is_valid_vector( vector ) ) {
+    return RTEMS_INVALID_ID;
+  }
+
+  if ( cpu_index >= rtems_configuration_get_maximum_processors() ) {
+    return RTEMS_NOT_CONFIGURED;
+  }
+
+#if defined(RTEMS_SMP)
+  if ( !_Processor_mask_Is_set( _SMP_Get_online_processors(), cpu_index ) ) {
+    return RTEMS_INCORRECT_STATE;
+  }
+
+  return bsp_interrupt_raise_on( vector, cpu_index );
+#else
+  return bsp_interrupt_raise( vector );
+#endif
+}
+
+rtems_status_code rtems_interrupt_clear( rtems_vector_number vector )
+{
+  if ( !bsp_interrupt_is_valid_vector( vector ) ) {
+    return RTEMS_INVALID_ID;
+  }
+
+  return bsp_interrupt_clear( vector );
+}