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| author | Moyano, Gabriel <gabriel.moyano@dlr.de> | 2021-04-09 08:28:40 +0200 |
|---|---|---|
| committer | Jan Sommer <jan.sommer@dlr.de> | 2021-04-16 08:46:17 +0200 |
| commit | 5728e8e3565ef6ffe56702b05077f4788e6eb055 (patch) | |
| tree | 8bcef2d1db6677899221a5643125a516d8f7e33c /bsps/shared/grlib/irq/genirq.c | |
| parent | smpfatal08: block secondary processors (diff) | |
| download | rtems-5728e8e3565ef6ffe56702b05077f4788e6eb055.tar.bz2 | |
grlib/genirq: Taking into account that it could be more than one ISR enabled/disabled
Diffstat (limited to 'bsps/shared/grlib/irq/genirq.c')
| -rw-r--r-- | bsps/shared/grlib/irq/genirq.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/bsps/shared/grlib/irq/genirq.c b/bsps/shared/grlib/irq/genirq.c index 285416b0d3..ca80445c70 100644 --- a/bsps/shared/grlib/irq/genirq.c +++ b/bsps/shared/grlib/irq/genirq.c @@ -188,8 +188,8 @@ static int genirq_set_active( return 1; } e = isrentry; - } else { - enabled += isrentry->enabled; + } else if ( isrentry->enabled ) { + enabled = 1; } isrentry = isrentry->next; } |