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authorSebastian Huber <sebastian.huber@embedded-brains.de>2022-03-14 15:04:51 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2022-04-06 09:48:51 +0200
commit9abcaaebc385addaeb06db8d3f2d0dc79695cebf (patch)
tree8047d08924d50d7a3aac3e2b0cad3d37438f289f /bsps/shared/dev/irq
parentunit: Test red-black trees (diff)
downloadrtems-9abcaaebc385addaeb06db8d3f2d0dc79695cebf.tar.bz2
bsps: Add <dev/irq/arm-gicv3.h>
Separate the Interrupt Manager implementation from the generic Arm GICv3 support. Move parts of the Arm GICv3 support into a new header file. This helps to support systems with a clustered structure in which multiple GICv3 instances are present. For example, two clusters of two Cortex-R52 cores where each cluster has a dedicated GICv3 instance.
Diffstat (limited to 'bsps/shared/dev/irq')
-rw-r--r--bsps/shared/dev/irq/arm-gicv3.c122
1 files changed, 1 insertions, 121 deletions
diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c
index afe21a8e15..58f97c4f43 100644
--- a/bsps/shared/dev/irq/arm-gicv3.c
+++ b/bsps/shared/dev/irq/arm-gicv3.c
@@ -25,132 +25,12 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <dev/irq/arm-gic.h>
-#include <dev/irq/arm-gic-arch.h>
+#include <dev/irq/arm-gicv3.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
#include <bsp/start.h>
-#ifdef ARM_MULTILIB_ARCH_V4
-#include <rtems/score/armv4.h>
-#else
-#include <rtems/score/cpu_irq.h>
-#endif
-
-#define PRIORITY_DEFAULT 127
-
-#define MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23)
-#define MPIDR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 16, 23)
-#define MPIDR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
-#define MPIDR_AFFINITY1(val) BSP_FLD64(val, 8, 15)
-#define MPIDR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 8, 15)
-#define MPIDR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15)
-#define MPIDR_AFFINITY0(val) BSP_FLD64(val, 0, 7)
-#define MPIDR_AFFINITY0_GET(reg) BSP_FLD64GET(reg, 0, 7)
-#define MPIDR_AFFINITY0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7)
-
-#define ICC_SGIR_AFFINITY3(val) BSP_FLD64(val, 48, 55)
-#define ICC_SGIR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 48, 55)
-#define ICC_SGIR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 48, 55)
-#define ICC_SGIR_IRM BSP_BIT32(40)
-#define ICC_SGIR_AFFINITY2(val) BSP_FLD64(val, 32, 39)
-#define ICC_SGIR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 32, 39)
-#define ICC_SGIR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
-#define ICC_SGIR_INTID(val) BSP_FLD64(val, 24, 27)
-#define ICC_SGIR_INTID_GET(reg) BSP_FLD64GET(reg, 24, 27)
-#define ICC_SGIR_INTID_SET(reg, val) BSP_FLD64SET(reg, val, 24, 27)
-#define ICC_SGIR_AFFINITY1(val) BSP_FLD64(val, 16, 23)
-#define ICC_SGIR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 16, 23)
-#define ICC_SGIR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
-#define ICC_SGIR_CPU_TARGET_LIST(val) BSP_FLD64(val, 0, 15)
-#define ICC_SGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD64GET(reg, 0, 15)
-#define ICC_SGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD64SET(reg, val, 0, 15)
-
-#ifdef ARM_MULTILIB_ARCH_V4
-/* cpuif->iccicr */
-#define ICC_CTLR "p15, 0, %0, c12, c12, 4"
-
-/* cpuif->iccpmr */
-#define ICC_PMR "p15, 0, %0, c4, c6, 0"
-
-/* cpuif->iccbpr */
-#define ICC_BPR0 "p15, 0, %0, c12, c8, 3"
-#define ICC_BPR1 "p15, 0, %0, c12, c12, 3"
-
-/* cpuif->icciar */
-#define ICC_IAR0 "p15, 0, %0, c12, c8, 0"
-#define ICC_IAR1 "p15, 0, %0, c12, c12, 0"
-
-/* cpuif->icceoir */
-#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1"
-#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1"
-
-#define ICC_SRE "p15, 0, %0, c12, c12, 5"
-
-#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6"
-#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7"
-
-#define MPIDR "p15, 0, %0, c0, c0, 5"
-
-#define READ_SR(SR_NAME) \
-({ \
- uint32_t value; \
- __asm__ volatile("mrc " SR_NAME : "=r" (value) ); \
- value; \
-})
-
-#define WRITE_SR(SR_NAME, VALUE) \
- __asm__ volatile("mcr " SR_NAME " \n" : : "r" (VALUE) );
-
-#define ICC_SGI1 "p15, 0, %Q0, %R0, c12"
-#define WRITE64_SR(SR_NAME, VALUE) \
- __asm__ volatile("mcrr " SR_NAME " \n" : : "r" (VALUE) );
-
-#else /* ARM_MULTILIB_ARCH_V4 */
-
-/* AArch64 GICv3 registers are not named in GCC */
-#define ICC_IGRPEN0 "S3_0_C12_C12_6, %0"
-#define ICC_IGRPEN1 "S3_0_C12_C12_7, %0"
-#define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7, %0"
-#define ICC_PMR "S3_0_C4_C6_0, %0"
-#define ICC_EOIR1 "S3_0_C12_C12_1, %0"
-#define ICC_SRE "S3_0_C12_C12_5, %0"
-#define ICC_BPR0 "S3_0_C12_C8_3, %0"
-#define ICC_CTLR "S3_0_C12_C12_4, %0"
-#define ICC_IAR1 "%0, S3_0_C12_C12_0"
-#define MPIDR "%0, mpidr_el1"
-#define MPIDR_AFFINITY3(val) BSP_FLD64(val, 32, 39)
-#define MPIDR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 32, 39)
-#define MPIDR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
-
-#define ICC_SGI1 "S3_0_C12_C11_5, %0"
-#define WRITE64_SR(SR_NAME, VALUE) \
- __asm__ volatile("msr " SR_NAME " \n" : : "r" (VALUE) );
-#define WRITE_SR(SR_NAME, VALUE) WRITE64_SR(SR_NAME, VALUE)
-
-#define READ_SR(SR_NAME) \
-({ \
- uint64_t value; \
- __asm__ volatile("mrs " SR_NAME : "=&r" (value) ); \
- value; \
-})
-
-
-#endif /* ARM_MULTILIB_ARCH_V4 */
-
-static volatile gic_redist *gicv3_get_redist(uint32_t cpu_index)
-{
- return (volatile gic_redist *)
- ((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000);
-}
-
-static volatile gic_sgi_ppi *gicv3_get_sgi_ppi(uint32_t cpu_index)
-{
- return (volatile gic_sgi_ppi *)
- ((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000 + 0x10000);
-}
-
void bsp_interrupt_dispatch(void)
{
uint32_t icciar = READ_SR(ICC_IAR1);