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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-19 12:11:19 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-25 10:07:43 +0200 |
| commit | 8db3f0e878b7f008ad05716f501220509662e2c4 (patch) | |
| tree | d55db59defa95096a3ef156427822a9f8744ab58 /bsps/riscv/riscv/start/start.S | |
| parent | riscv: New CPU_Exception_frame (diff) | |
| download | rtems-8db3f0e878b7f008ad05716f501220509662e2c4.tar.bz2 | |
riscv: Rework exception handling
Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions. Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.
Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.
Update #3433.
Diffstat (limited to '')
| -rw-r--r-- | bsps/riscv/riscv/start/start.S | 37 |
1 files changed, 3 insertions, 34 deletions
diff --git a/bsps/riscv/riscv/start/start.S b/bsps/riscv/riscv/start/start.S index 0dad170c3c..83926a9272 100644 --- a/bsps/riscv/riscv/start/start.S +++ b/bsps/riscv/riscv/start/start.S @@ -1,4 +1,6 @@ /* + * Copyright (c) 2018 embedded brains GmbH + * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> * @@ -33,13 +35,6 @@ #include <bsp/linker-symbols.h> #include <bspopts.h> -EXTERN(bsp_section_bss_begin) -EXTERN(bsp_section_bss_end) -EXTERN(ISR_Handler) -EXTERN(bsp_section_stack_begin) - -PUBLIC(bsp_start_vector_table_begin) -PUBLIC(bsp_start_vector_table_end) PUBLIC(_start) .section .bsp_start_text, "wax", @progbits @@ -70,7 +65,7 @@ SYM(_start): call bsp_fdt_copy #endif - LADDR t0, ISR_Handler + LADDR t0, _RISCV_Exception_handler csrw mtvec, t0 /* Clear .bss */ @@ -107,29 +102,3 @@ SYM(_start): .Lsecondary_processor_go: .word 0xdeadbeef #endif - -#if __riscv_xlen == 32 -#define ADDR .word -#elif __riscv_xlen == 64 -#define ADDR .quad -#endif - - .align 4 -bsp_start_vector_table_begin: - ADDR _RISCV_Exception_default /* User int */ - ADDR _RISCV_Exception_default /* Supervisor int */ - ADDR _RISCV_Exception_default /* Reserved */ - ADDR _RISCV_Exception_default /* Machine int */ - ADDR _RISCV_Exception_default /* User timer int */ - ADDR _RISCV_Exception_default /* Supervisor Timer int */ - ADDR _RISCV_Exception_default /* Reserved */ - ADDR _RISCV_Exception_default /* Machine Timer int */ - ADDR _RISCV_Exception_default /* User external int */ - ADDR _RISCV_Exception_default /* Supervisor external int */ - ADDR _RISCV_Exception_default /* Reserved */ - ADDR _RISCV_Exception_default /* Machine external int */ - ADDR _RISCV_Exception_default - ADDR _RISCV_Exception_default - ADDR _RISCV_Exception_default - ADDR _RISCV_Exception_default -bsp_start_vector_table_end: |