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author | Pragnesh Patel <pragnesh.patel@sifive.com> | 2019-10-22 10:20:05 +0000 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2019-10-23 08:11:50 +0200 |
commit | a7f5e42cc5234f239a01b8f69847ebb018710948 (patch) | |
tree | 75d1abe5128bc54b678580c7d2d03b6823568e70 /bsps/riscv/riscv/start/bspstart.c | |
parent | libdebugger/arm: Clean up the building on arm variants. (diff) | |
download | rtems-a7f5e42cc5234f239a01b8f69847ebb018710948.tar.bz2 |
riscv: add freedom E310 Arty A7 bsp
Added support for Sifive Freedom FE310 soc on Arty A7 FPGA board.
Update #3785.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Diffstat (limited to '')
-rw-r--r-- | bsps/riscv/riscv/start/bspstart.c | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/bsps/riscv/riscv/start/bspstart.c b/bsps/riscv/riscv/start/bspstart.c index d4c4e1ff7f..a462bbe6e1 100644 --- a/bsps/riscv/riscv/start/bspstart.c +++ b/bsps/riscv/riscv/start/bspstart.c @@ -30,6 +30,11 @@ #include <bsp/riscv.h> #include <libfdt.h> +#include <string.h> + +#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 +unsigned int riscv_core_freq; +#endif void *riscv_fdt_get_address(const void *fdt, int node) { @@ -161,8 +166,55 @@ uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle) return UINT32_MAX; } +#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 +static uint32_t get_core_frequency(void) +{ + uint32_t node; + const char *fdt=bsp_fdt_get(); + + char *tlclk; + uint32_t len; + + do + { + node=fdt_node_offset_by_compatible(fdt, -1,"fixed-clock"); + uint32_t *val=NULL; + if (node>0) + { + tlclk = fdt_getprop(fdt, node, "clock-output-names", &len); + + if (strcmp(tlclk,"tlclk") == 0) + { + val = fdt_getprop(fdt, node, "clock-frequency", &len); + if(val !=NULL) + { + riscv_core_freq=fdt32_to_cpu(*val); + break; + } + } + }else + { + bsp_fatal(RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE); + } + + } while (node > 0); + + return riscv_core_freq; +} + +inline uint32_t riscv_get_core_frequency(void) +{ + return riscv_core_freq; +} +#endif + void bsp_start(void) { riscv_find_harts(); bsp_interrupt_initialize(); + +#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 + riscv_core_freq=get_core_frequency(); +#endif + } |