diff options
| author | Padmarao Begari <padmarao.begari@microchip.com> | 2022-09-19 18:30:26 +0530 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2022-09-20 12:00:51 -0500 |
| commit | 6b0d3c987349d188b65e9fc8229daeba247928c5 (patch) | |
| tree | 4f6f37aaab9be619b82612eb4f000a42549488ca /bsps/riscv/riscv/start/bspstart.c | |
| parent | spec/build/bsps: Add dtb support (diff) | |
| download | rtems-6b0d3c987349d188b65e9fc8229daeba247928c5.tar.bz2 | |
bsps/riscv: Add Microchip PolarFire SoC BSP variant
The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
Diffstat (limited to '')
| -rw-r--r-- | bsps/riscv/riscv/start/bspstart.c | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/bsps/riscv/riscv/start/bspstart.c b/bsps/riscv/riscv/start/bspstart.c index d33e9965f8..66e2934013 100644 --- a/bsps/riscv/riscv/start/bspstart.c +++ b/bsps/riscv/riscv/start/bspstart.c @@ -74,6 +74,10 @@ void *riscv_fdt_get_address(const void *fdt, int node) return (void *)(uintptr_t) addr; } +#if RISCV_ENABLE_MPFS_SUPPORT != 0 +uint32_t riscv_hart_count; +static uint32_t riscv_hart_phandles[5]; +#else #ifdef RTEMS_SMP uint32_t riscv_hart_count; @@ -81,6 +85,7 @@ static uint32_t riscv_hart_phandles[CPU_MAXIMUM_PROCESSORS]; #else static uint32_t riscv_hart_phandles[1]; #endif +#endif static void riscv_find_harts(void) { @@ -146,9 +151,13 @@ static void riscv_find_harts(void) riscv_hart_phandles[hart_index] = phandle; } +#if RISCV_ENABLE_MPFS_SUPPORT != 0 + riscv_hart_count = max_hart_index + 1; +#else #ifdef RTEMS_SMP riscv_hart_count = max_hart_index + 1; #endif +#endif } uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle) @@ -166,7 +175,7 @@ uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle) static uint32_t get_core_frequency(void) { -#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 +#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 || RISCV_ENABLE_MPFS_SUPPORT != 0 uint32_t node; const char *fdt; const char *tlclk; @@ -177,7 +186,13 @@ static uint32_t get_core_frequency(void) node = fdt_node_offset_by_compatible(fdt, -1,"fixed-clock"); tlclk = fdt_getprop(fdt, node, "clock-output-names", &len); - if (strcmp(tlclk,"tlclk") != 0) { +#if RISCV_ENABLE_FRDME310ARTY_SUPPORT != 0 + if (strcmp(tlclk,"tlclk") != 0) +#endif +#if RISCV_ENABLE_MPFS_SUPPORT != 0 + if (strcmp(tlclk,"msspllclk") != 0) +#endif + { bsp_fatal(RISCV_FATAL_NO_TLCLOCK_FREQUENCY_IN_DEVICE_TREE); } |