bsps/riscv: add riscv/kendrytek210 BSP variant source changes

This patch adds support for the Kendryte K210 RISC-V BSP variant.
The SoC uses the existing Interrupt Controller, Timer, and console UART.
It only needs SoC specific initialization and an embedded device tree binary
similar to the polarfire SoC BSP.

Updates #4876

1 files changed, 43 insertions, 0 deletions

diff --git a/bsps/riscv/riscv/start/bspstart.c b/bsps/riscv/riscv/start/bspstart.c
index f27713b5bf..fa1e978dc7 100644
--- a/bsps/riscv/riscv/start/bspstart.c
+++ b/bsps/riscv/riscv/start/bspstart.c
@@ -209,7 +209,16 @@ static uint32_t get_core_frequency(void)
     return fdt32_to_cpu(*val);
   }
 #endif
+
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+  uint32_t cpu_clock;
+
+  cpu_clock = k210_get_frequency();
+  return cpu_clock;
+#else
   return 0;
+#endif
+
 }
 
 uint32_t riscv_get_core_frequency(void)
@@ -223,6 +232,40 @@ uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
   return RISCV_INTERRUPT_VECTOR_EXTERNAL(intr[0]);
 }
 
+#if RISCV_ENABLE_KENDRYTE_K210_SUPPORT != 0
+uint32_t k210_get_frequency(void)
+{
+  k210_sysctl_t *sysctl = (k210_sysctl_t *)K210_SYSCTL_BASE;
+  uint32_t cpu_clock = 0;
+  uint32_t clk_freq;
+  uint32_t pll0, nr, nf, od;
+  uint32_t node;
+  const char *fdt;
+  const fdt32_t *val;
+  int len;
+
+  fdt = bsp_fdt_get();
+  node = fdt_node_offset_by_compatible(fdt, -1,"fixed-clock");
+  val = fdt_getprop(fdt, node, "clock-frequency", &len);
+  if (val != NULL && len == 4) {
+    clk_freq = fdt32_to_cpu(*val);
+
+    if (CLKSEL0_ACLK_SEL(sysctl->clk_sel0) == 1) {
+       /* PLL0 selected */
+       pll0 = sysctl->pll0;
+       nr = PLL_CLK_R(pll0) + 1;
+       nf = PLL_CLK_F(pll0) + 1;
+       od = PLL_CLK_OD(pll0) + 1;
+       cpu_clock = (clk_freq / nr * nf / od)/2;
+    } else {
+       /* OSC selected */
+       cpu_clock = clk_freq;
+    }
+  }
+  return cpu_clock;
+}
+#endif
+
 void bsp_start(void)
 {
   riscv_find_harts();