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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-20 13:11:04 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-25 10:07:44 +0200 |
| commit | 447fd894aeb245959627893e138b2b9640486040 (patch) | |
| tree | ded0b8d93a11d4ef7d577607e0e800f33879b5d1 /bsps/riscv/riscv/include/bsp/riscv.h | |
| parent | riscv: Add CLINT and PLIC support (diff) | |
| download | rtems-447fd894aeb245959627893e138b2b9640486040.tar.bz2 | |
bsp/riscv: Add basic SMP startup
Update #3433.
Diffstat (limited to '')
| -rw-r--r-- | bsps/riscv/riscv/include/bsp/riscv.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/bsps/riscv/riscv/include/bsp/riscv.h b/bsps/riscv/riscv/include/bsp/riscv.h index b85b250526..6701bb6cc6 100644 --- a/bsps/riscv/riscv/include/bsp/riscv.h +++ b/bsps/riscv/riscv/include/bsp/riscv.h @@ -28,12 +28,24 @@ #include <bsp.h> +#include <rtems/score/cpuimpl.h> + #ifdef __cplusplus extern "C" { #endif +extern volatile RISCV_CLINT_regs *riscv_clint; + void *riscv_fdt_get_address(const void *fdt, int node); +#ifdef RTEMS_SMP +extern uint32_t riscv_hart_count; + +extern uint32_t riscv_hart_phandles[CPU_MAXIMUM_PROCESSORS]; + +uint32_t riscv_get_hart_index_by_phandle(uint32_t phandle); +#endif + #if RISCV_ENABLE_HTIF_SUPPORT != 0 void htif_poweroff(void); #endif |