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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-24 13:27:54 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-25 10:07:44 +0200 |
| commit | adede135e7fefc1ba2020ff2d64da3f4185ba85c (patch) | |
| tree | e20625196322c3d994a6498e1d3085de3304cd9f /bsps/riscv/riscv/include/bsp/irq.h | |
| parent | bsp/riscv: Add simple SMP support to clock driver (diff) | |
| download | rtems-adede135e7fefc1ba2020ff2d64da3f4185ba85c.tar.bz2 | |
bsp/riscv: Add PLIC support
Update #3433.
Diffstat (limited to '')
| -rw-r--r-- | bsps/riscv/riscv/include/bsp/irq.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/bsps/riscv/riscv/include/bsp/irq.h b/bsps/riscv/riscv/include/bsp/irq.h index 353005fadf..cf88443740 100644 --- a/bsps/riscv/riscv/include/bsp/irq.h +++ b/bsps/riscv/riscv/include/bsp/irq.h @@ -42,6 +42,7 @@ #include <bsp.h> #include <rtems/irq.h> #include <rtems/irq-extension.h> +#include <rtems/score/processormask.h> #define RISCV_INTERRUPT_VECTOR_SOFTWARE 0 @@ -49,10 +50,24 @@ #define RISCV_INTERRUPT_VECTOR_EXTERNAL(x) ((x) + 2) +#define RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(x) ((x) >= 2) + +#define RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(x) ((x) - 2) + #define BSP_INTERRUPT_VECTOR_MIN 0 #define BSP_INTERRUPT_VECTOR_MAX RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS - 1) +void bsp_interrupt_set_affinity( + rtems_vector_number vector, + const Processor_mask *affinity +); + +void bsp_interrupt_get_affinity( + rtems_vector_number vector, + Processor_mask *affinity +); + #endif /* ASM */ #endif /* LIBBSP_GENERIC_RISCV_IRQ_H */ |