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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-22 07:10:44 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-27 08:58:17 +0200 |
| commit | f3da074a120b644da501152c5ccb08c5fd5bd19c (patch) | |
| tree | 15c3f6079258830800000635f47ae64cb44e48c3 /bsps/riscv/riscv/config/rv64imafdc_medany.cfg | |
| parent | bsp/riscv_generic: Rename to "riscv" (diff) | |
| download | rtems-f3da074a120b644da501152c5ccb08c5fd5bd19c.tar.bz2 | |
bsp/riscv: Add new BSP variants
The latest RISC-V tool chain introduced new multilib variants. Add
corresponding BSP variants.
Update #3433.
Diffstat (limited to '')
| -rw-r--r-- | bsps/riscv/riscv/config/rv64imafdc_medany.cfg | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/bsps/riscv/riscv/config/rv64imafdc_medany.cfg b/bsps/riscv/riscv/config/rv64imafdc_medany.cfg new file mode 100644 index 0000000000..b04e78b0e9 --- /dev/null +++ b/bsps/riscv/riscv/config/rv64imafdc_medany.cfg @@ -0,0 +1,9 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = riscv + +CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d -mcmodel=medany + +LDFLAGS = -Wl,--gc-sections + +CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections |