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| author | Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk> | 2019-10-24 13:05:07 +0100 |
|---|---|---|
| committer | Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk> | 2019-10-27 10:45:31 +0000 |
| commit | 94481cedc4165f6a49ef5287098251740922fee1 (patch) | |
| tree | eb670b27125bfc5da7e4b5869f77d64287726658 /bsps/riscv/riscv/config/rv64imafdc_clang.cfg | |
| parent | riscv: Add new offending input sections to the linker script (diff) | |
| download | rtems-94481cedc4165f6a49ef5287098251740922fee1.tar.bz2 | |
riscv: Add new BSP cfg variants to be built with llvm/clang
Diffstat (limited to '')
| -rw-r--r-- | bsps/riscv/riscv/config/rv64imafdc_clang.cfg | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/bsps/riscv/riscv/config/rv64imafdc_clang.cfg b/bsps/riscv/riscv/config/rv64imafdc_clang.cfg new file mode 100644 index 0000000000..ec668bcb18 --- /dev/null +++ b/bsps/riscv/riscv/config/rv64imafdc_clang.cfg @@ -0,0 +1,14 @@ +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = riscv + +CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d + +# Clang-related flags +CPU_CFLAGS += -target riscv64-unknown-rtems6 --sysroot=$(NEWLIB_SYSROOT) + +LDFLAGS = -Wl,--gc-sections -L$(RTEMS_BSP_LIBBSP_PATH) -L$(PROJECT_LIB) -L$(RTEMS_BSP_ARCH_LINKCMDS_PATH) + +# Clang-related flags + +CFLAGS_OPTIMIZE_V ?= -O0 -g -ffunction-sections -fdata-sections |