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| author | Chris Johns <chrisj@rtems.org> | 2021-02-15 12:27:14 -1000 |
|---|---|---|
| committer | Chris Johns <chrisj@rtems.org> | 2021-02-16 09:40:47 +1100 |
| commit | 026eb3db7e61ed29ff3b676c126168bf08dfe0a8 (patch) | |
| tree | fe934079765217b7cded090a787f31df4655a2eb /bsps/powerpc/motorola_powerpc/start/bspstart.c | |
| parent | powerpc/motorola_powerpc: Enable bus PCI support in LibBSD (diff) | |
| download | rtems-026eb3db7e61ed29ff3b676c126168bf08dfe0a8.tar.bz2 | |
powerpc/motorola_powerpc: Add cache coherent memory to the allocator
Updates #4245
Updates #4243
Diffstat (limited to 'bsps/powerpc/motorola_powerpc/start/bspstart.c')
| -rw-r--r-- | bsps/powerpc/motorola_powerpc/start/bspstart.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/bsps/powerpc/motorola_powerpc/start/bspstart.c b/bsps/powerpc/motorola_powerpc/start/bspstart.c index ef8418e2c6..a781297565 100644 --- a/bsps/powerpc/motorola_powerpc/start/bspstart.c +++ b/bsps/powerpc/motorola_powerpc/start/bspstart.c @@ -44,6 +44,9 @@ extern void set_L2CR(unsigned); extern Triv121PgTbl BSP_pgtbl_setup(unsigned int *); extern void BSP_pgtbl_activate(Triv121PgTbl); +#define PPC_MIN_BAT_SIZE (128 * 1024) +static char cc_memory[PPC_MIN_BAT_SIZE] RTEMS_ALIGNED(PPC_MIN_BAT_SIZE); + SPR_RW(SPRG1) #if defined(DEBUG_BATS) @@ -351,6 +354,9 @@ static void bsp_early( void ) setdbat(3, 0, 0, 0, 0); } + setdbat(3, (intptr_t) &cc_memory[0], (intptr_t) &cc_memory[0], PPC_MIN_BAT_SIZE, IO_PAGE); + rtems_cache_coherent_add_area(&cc_memory[0], PPC_MIN_BAT_SIZE); + #if defined(DEBUG_BATS) ShowBATS(); #endif |