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| author | Alex White <alex.white@oarcorp.com> | 2021-09-30 23:57:01 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2021-10-13 14:45:37 -0500 |
| commit | d03776e804e2cb190442d2a2debf297714ca8049 (patch) | |
| tree | 108aba7fb973915a52c407751ce23abf77eccac6 /bsps/microblaze/shared/start/start.S | |
| parent | bsps: Add MicroBlaze FPGA BSP (diff) | |
| download | rtems-d03776e804e2cb190442d2a2debf297714ca8049.tar.bz2 | |
microblaze: Rework for RTEMS 6
This reworks the existing MicroBlaze architecture port and BSP to
achieve basic functionality using the latest RTEMS APIs.
Diffstat (limited to '')
| -rw-r--r-- | bsps/microblaze/shared/start/start.S (renamed from c/src/lib/libbsp/microblaze/microblaze_fpga/start/start.S) | 95 |
1 files changed, 50 insertions, 45 deletions
diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/start/start.S b/bsps/microblaze/shared/start/start.S index bb3dc3dd65..97250f9316 100644 --- a/c/src/lib/libbsp/microblaze/microblaze_fpga/start/start.S +++ b/bsps/microblaze/shared/start/start.S @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without @@ -34,76 +36,79 @@ Address Vector type Label ------- ----------- ------ - # 0x00 # (-- IMM --) - # 0x04 # Reset _start1 + # 0x00 # (-- IMM --) + # 0x04 # Reset _start1 - # 0x08 # (-- IMM --) - # 0x0c # Software Exception _exception_handler + # 0x08 # (-- IMM --) + # 0x0c # Software Exception _exception_handler - # 0x10 # (-- IMM --) - # 0x14 # Hardware Interrupt _interrupt_handler + # 0x10 # (-- IMM --) + # 0x14 # Hardware Interrupt _interrupt_handler - # 0x18 # (-- IMM --) - # 0x1C # Breakpoint Exception (-- Don't Care --) + # 0x18 # (-- IMM --) + # 0x1C # Breakpoint Exception (-- Don't Care --) - # 0x20 # (-- IMM --) - # 0x24 # Hardware Exception _hw_exception_handler + # 0x20 # (-- IMM --) + # 0x24 # Hardware Exception _hw_exception_handler */ .globl _start - .section .vectors.reset, "ax" + .section .vectors.reset, "ax" .align 2 - .ent _start - .type _start, @function + .ent _start + .type _start, @function _start: - brai _start1 - .end _start + brai _start1 + .end _start - .section .vectors.sw_exception, "ax" - .align 2 + .section .vectors.sw_exception, "ax" + .align 2 _vector_sw_exception: - brai _exception_handler + brai _exception_handler - .section .vectors.interrupt, "ax" - .align 2 + .section .vectors.interrupt, "ax" + .align 2 _vector_interrupt: - brai _interrupt_handler + brai _interrupt_handler - .section .vectors.hw_exception, "ax" - .align 2 + .section .vectors.hw_exception, "ax" + .align 2 _vector_hw_exception: - brai _hw_exception_handler + brai _hw_exception_handler - .section .text - .globl _start1 - .align 2 - .ent _start1 - .type _start1, @function + .section .text + .globl _start1 + .align 2 + .ent _start1 + .type _start1, @function _start1: - //la r13, r0, _SDA_BASE_ /* Set the Small Data Anchors and the stack pointer */ - //la r2, r0, _SDA2_BASE_ - la r1, r0, bsp_section_stack_begin-16 /* 16 bytes (4 words are needed by crtinit for args and link reg */ + //la r13, r0, _SDA_BASE_ /* Set the Small Data Anchors and the stack pointer */ + //la r2, r0, _SDA2_BASE_ + la r1, r0, _ISR_Stack_area_end-16 /* 16 bytes (4 words are needed by crtinit for args and link reg */ - brlid r15, _crtinit /* Initialize BSS and run program */ + brlid r15, _crtinit /* Initialize BSS and run program */ nop - brlid r15, exit /* Call exit with the return value of main */ - addik r5, r3, 0 - - /* Control does not reach here */ - .end _start1 +#ifndef __rtems__ + brlid r15, exit /* Call exit with the return value of main */ + addik r5, r3, 0 +#endif /* __rtems__ */ + /* Control does not reach here */ + .end _start1 +#ifndef __rtems__ /* - _exit - Our simple _exit + _exit + Our simple _exit */ - .globl _exit - .align 2 - .ent _exit - .type _exit, @function + .globl _exit + .align 2 + .ent _exit + .type _exit, @function _exit: - bri 0 + bri 0 .end _exit +#endif /* __rtems__ */ |