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authorAlex White <alex.white@oarcorp.com>2021-12-23 17:33:39 -0600
committerJoel Sherrill <joel@rtems.org>2022-02-01 16:58:24 -0600
commit37543e196813e552fa316cf595f26e1ac612e34a (patch)
tree3f700b07df48cb9ce23ae607648c227313dc067a /bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S
parentmicroblaze: Add support for libbsd. (diff)
downloadrtems-37543e196813e552fa316cf595f26e1ac612e34a.tar.bz2
microblaze: Add support for libbsd networking
This includes fixes and improvements necessary to get libbsd networking running.
Diffstat (limited to '')
-rw-r--r--bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S20
1 files changed, 20 insertions, 0 deletions
diff --git a/bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S b/bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S
new file mode 100644
index 0000000000..78babf0176
--- /dev/null
+++ b/bsps/microblaze/microblaze_fpga/start/microblaze_enable_dcache.S
@@ -0,0 +1,20 @@
+/******************************************************************************
+* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+ .text
+ .globl microblaze_enable_dcache
+ .ent microblaze_enable_dcache
+ .align 2
+microblaze_enable_dcache:
+ /* Read the MSR register */
+ mfs r8, rmsr
+ /* Set the interrupt enable bit */
+ ori r8, r8, 0x80
+ /* Save the MSR register */
+ mts rmsr, r8
+ /* Return */
+ rtsd r15, 8
+ nop
+ .end microblaze_enable_dcache