diff options
| author | Karel Gardas <karel@functional.vision> | 2022-05-16 14:53:57 +0200 |
|---|---|---|
| committer | Karel Gardas <karel@functional.vision> | 2022-06-01 11:20:49 +0200 |
| commit | ec39a695296e5fdda342c0d99abcce2a8210d0c1 (patch) | |
| tree | 075757093ba490c91147c328f0466e80c725ca14 /bsps/arm | |
| parent | bsps/arm: add CMSIS Cortex-M4 Core Peripheral Access Layer Header File (diff) | |
| download | rtems-ec39a695296e5fdda342c0d99abcce2a8210d0c1.tar.bz2 | |
bsps/stm32h7: enable cache and MPU only on Cortex-M7
Sponsored-By: Precidata
Diffstat (limited to 'bsps/arm')
| -rw-r--r-- | bsps/arm/stm32h7/start/bspstarthooks.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/bsps/arm/stm32h7/start/bspstarthooks.c b/bsps/arm/stm32h7/start/bspstarthooks.c index ef26af5eba..54df5a2da8 100644 --- a/bsps/arm/stm32h7/start/bspstarthooks.c +++ b/bsps/arm/stm32h7/start/bspstarthooks.c @@ -102,6 +102,7 @@ void bsp_start_hook_0(void) SystemInit_ExtMemCtl(); } +#if __CORTEX_M == 0x07U if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) { SCB_EnableICache(); } @@ -111,12 +112,15 @@ void bsp_start_hook_0(void) } _ARMV7M_MPU_Setup(stm32h7_config_mpu_region, stm32h7_config_mpu_region_count); +#endif } void bsp_start_hook_1(void) { bsp_start_copy_sections_compact(); +#if __CORTEX_M == 0x07U SCB_CleanDCache(); SCB_InvalidateICache(); +#endif bsp_start_clear_bss(); } |