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| author | Jonathan Brandmeyer <jbrandmeyer@planetiq.com> | 2019-03-01 11:21:52 -0700 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2019-03-08 07:39:42 +0100 |
| commit | b1ac3a57709b05545b7b24dc71a497d117dbc582 (patch) | |
| tree | 33e08d70da798926b5950398db87a7347a368852 /bsps/arm | |
| parent | bsps/powerpc: Move mpc55xx header files (diff) | |
| download | rtems-b1ac3a57709b05545b7b24dc71a497d117dbc582.tar.bz2 | |
cpukit/arm: Correct register definition
The register definition for the CP15 PMCR (performance monitor control
register) has the bits for X (export enable) and D (clock divider
enable) backwards. Correct them according to ARMv7-A/R Architecture
Reference Manual, Rev C, Section B4.1.117.
Consequences: On an implementation that starts off with D set at reset,
the clock divider will not be disabled by using RTEMS' definition of the
D bit.
Tested by using the counter on Xilinx Zynq 7020 to measure some atomic
accesses and cache flushing operations.
Diffstat (limited to 'bsps/arm')
0 files changed, 0 insertions, 0 deletions