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authorSebastian Huber <sebastian.huber@embedded-brains.de>2021-07-09 10:39:01 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2021-07-09 10:43:10 +0200
commit7b2d5699be47e6847e8880ab3956024ae3aaaed7 (patch)
treeb813b6c6b845ef04c831ed113efa9cd26d1f9d11 /bsps/arm
parentbsps/arm: Fix SMP start (diff)
downloadrtems-7b2d5699be47e6847e8880ab3956024ae3aaaed7.tar.bz2
bsp/imx: Fix SMP start
Flush imx_gic_dist_base so that secondary processors can use the right address.
Diffstat (limited to 'bsps/arm')
-rw-r--r--bsps/arm/imx/start/bspstart.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/bsps/arm/imx/start/bspstart.c b/bsps/arm/imx/start/bspstart.c
index 238bc2bd28..2f59f95752 100644
--- a/bsps/arm/imx/start/bspstart.c
+++ b/bsps/arm/imx/start/bspstart.c
@@ -153,6 +153,18 @@ static void imx_find_gic(const void *fdt)
node = fdt_path_offset(fdt, "/soc/interrupt-controller");
}
imx_gic_dist_base = (uintptr_t) imx_get_reg_of_node(fdt, node);
+
+#if defined(RTEMS_SMP)
+ /*
+ * Secondary processors start with a disabled data cache and use the GIC to
+ * deterine if they can continue the initialization, see
+ * arm_gic_irq_initialize_secondary_cpu().
+ */
+ rtems_cache_flush_multiple_data_lines(
+ &imx_gic_dist_base,
+ sizeof(imx_gic_dist_base)
+ );
+#endif
}
void bsp_start(void)