diff options
author | Christian Mauderer <christian.mauderer@embedded-brains.de> | 2021-03-02 14:00:50 +0100 |
---|---|---|
committer | Christian Mauderer <christian.mauderer@embedded-brains.de> | 2021-04-01 09:04:21 +0200 |
commit | aa9e3c621129c612ecfe90e34636aa0765e9a3ee (patch) | |
tree | a598e7125878bc6730b76465b9fcf3d24a3117dc /bsps/arm/stm32h7/start/stm32h7-hal.c | |
parent | bsps/xilinx_zynq: Add Xilinx AXI SPI driver to autotools build (diff) | |
download | rtems-aa9e3c621129c612ecfe90e34636aa0765e9a3ee.tar.bz2 |
stm32h7: Add SDMMC modules to clock
Update #4372
Diffstat (limited to '')
-rw-r--r-- | bsps/arm/stm32h7/start/stm32h7-hal.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/bsps/arm/stm32h7/start/stm32h7-hal.c b/bsps/arm/stm32h7/start/stm32h7-hal.c index 3dcc3098f4..d042a5b8c9 100644 --- a/bsps/arm/stm32h7/start/stm32h7-hal.c +++ b/bsps/arm/stm32h7/start/stm32h7-hal.c @@ -84,6 +84,12 @@ stm32h7_module_index stm32h7_get_module_index(const void *regs) #endif case RNG_BASE: return STM32H7_MODULE_RNG; + case SDMMC1_BASE: + case DLYB_SDMMC1_BASE: + return STM32H7_MODULE_SDMMC1; + case SDMMC2_BASE: + case DLYB_SDMMC2_BASE: + return STM32H7_MODULE_SDMMC2; } return STM32H7_MODULE_INVALID; @@ -132,7 +138,9 @@ static const stm32h7_clk_info stm32h7_clk[] = { [STM32H7_MODULE_USB1_OTG] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN }, [STM32H7_MODULE_USB1_OTG_ULPI] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN }, [STM32H7_MODULE_USB2_OTG] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN }, - [STM32H7_MODULE_USB2_OTG_ULPI] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN } + [STM32H7_MODULE_USB2_OTG_ULPI] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN }, + [STM32H7_MODULE_SDMMC1] = { &RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN }, + [STM32H7_MODULE_SDMMC2] = { &RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN }, }; void stm32h7_clk_enable(stm32h7_module_index index) @@ -203,7 +211,9 @@ static const stm32h7_clk_info stm32h7_clk_low_power[] = { [STM32H7_MODULE_USB1_OTG] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB1OTGHSLPEN }, [STM32H7_MODULE_USB1_OTG_ULPI] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB1OTGHSULPILPEN }, [STM32H7_MODULE_USB2_OTG] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB2OTGHSLPEN }, - [STM32H7_MODULE_USB2_OTG_ULPI] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB2OTGHSULPILPEN } + [STM32H7_MODULE_USB2_OTG_ULPI] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB2OTGHSULPILPEN }, + [STM32H7_MODULE_SDMMC1] = { &RCC->AHB3LPENR, RCC_AHB3LPENR_SDMMC1LPEN }, + [STM32H7_MODULE_SDMMC2] = { &RCC->AHB2LPENR, RCC_AHB2LPENR_SDMMC2LPEN }, }; void stm32h7_clk_low_power_enable(stm32h7_module_index index) |