bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

23 files changed, 1963 insertions, 0 deletions

diff --git a/bsps/arm/lpc24xx/start/bsp_specs b/bsps/arm/lpc24xx/start/bsp_specs
new file mode 100644
index 0000000000..47dd31d46b
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfiles)} %{qrtems: crtend.o%s crtn.o%s}
diff --git a/bsps/arm/lpc24xx/start/bspreset-armv4.c b/bsps/arm/lpc24xx/start/bspreset-armv4.c
new file mode 100644
index 0000000000..c53b4e2447
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/bspreset-armv4.c
@@ -0,0 +1,51 @@
+/**
+ * @file
+ *
+ * @ingroup lpc24xx
+ *
+ * @brief Reset code.
+ */
+
+/*
+ * Copyright (c) 2008-2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <rtems/score/armv7m.h>
+
+#include <bsp/bootcard.h>
+#include <bsp/lpc24xx.h>
+#include <bsp/start.h>
+
+#ifdef ARM_MULTILIB_ARCH_V4
+
+BSP_START_TEXT_SECTION __attribute__((flatten)) void bsp_reset(void)
+{
+  rtems_interrupt_level level;
+
+  (void) level;
+  rtems_interrupt_disable(level);
+
+  /* Trigger watchdog reset */
+  WDCLKSEL = 0;
+  WDTC = 0xff;
+  WDMOD = 0x3;
+  WDFEED = 0xaa;
+  WDFEED = 0x55;
+
+  while (true) {
+    /* Do nothing */
+  }
+}
+
+#endif /* ARM_MULTILIB_ARCH_V4 */
diff --git a/bsps/arm/lpc24xx/start/bspstart.c b/bsps/arm/lpc24xx/start/bspstart.c
new file mode 100644
index 0000000000..6f00f35f99
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/bspstart.c
@@ -0,0 +1,96 @@
+/**
+ * @file
+ *
+ * @ingroup lpc24xx
+ *
+ * @brief Startup code.
+ */
+
+/*
+ * Copyright (c) 2008-2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <bsp/dma.h>
+#include <bsp/io.h>
+#include <bsp/irq-generic.h>
+#include <bsp/irq.h>
+#include <bsp/linker-symbols.h>
+#include <bsp/lpc24xx.h>
+#include <bsp/system-clocks.h>
+#include <bsp/uart-output-char.h>
+
+#ifdef LPC24XX_HEAP_EXTEND
+  LINKER_SYMBOL(lpc24xx_region_heap_0_begin);
+  LINKER_SYMBOL(lpc24xx_region_heap_0_size);
+  LINKER_SYMBOL(lpc24xx_region_heap_0_end);
+
+  LINKER_SYMBOL(lpc24xx_region_heap_1_begin);
+  LINKER_SYMBOL(lpc24xx_region_heap_1_size);
+  LINKER_SYMBOL(lpc24xx_region_heap_1_end);
+
+  extern Heap_Control *RTEMS_Malloc_Heap;
+#endif
+
+static void heap_extend(void)
+{
+  #ifdef LPC24XX_HEAP_EXTEND
+    _Heap_Extend(
+      RTEMS_Malloc_Heap,
+      lpc24xx_region_heap_0_begin,
+      (uintptr_t) lpc24xx_region_heap_0_size,
+      0
+    );
+    _Heap_Extend(
+      RTEMS_Malloc_Heap,
+      lpc24xx_region_heap_1_begin,
+      (uintptr_t) lpc24xx_region_heap_1_size,
+      0
+    );
+  #endif
+}
+
+static void initialize_console(void)
+{
+  #ifdef LPC24XX_CONFIG_CONSOLE
+    static const lpc24xx_pin_range pins [] = {
+      LPC24XX_PIN_UART_0_TXD,
+      LPC24XX_PIN_UART_0_RXD,
+      LPC24XX_PIN_TERMINAL
+    };
+
+    lpc24xx_module_enable(LPC24XX_MODULE_UART_0, LPC24XX_MODULE_PCLK_DEFAULT);
+    lpc24xx_pin_config(&pins [0], LPC24XX_PIN_SET_FUNCTION);
+    BSP_CONSOLE_UART_INIT(LPC24XX_PCLK / 16 / LPC24XX_UART_BAUD);
+  #endif
+}
+
+void bsp_start(void)
+{
+  /* Initialize Timer 1 */
+  lpc24xx_module_enable(LPC24XX_MODULE_TIMER_1, LPC24XX_MODULE_PCLK_DEFAULT);
+
+  /* Initialize standard timer */
+  lpc24xx_timer_initialize();
+
+  initialize_console();
+
+  /* Interrupts */
+  bsp_interrupt_initialize();
+
+  /* DMA */
+  lpc24xx_dma_initialize();
+
+  heap_extend();
+}
diff --git a/bsps/arm/lpc24xx/start/bspstarthooks.c b/bsps/arm/lpc24xx/start/bspstarthooks.c
new file mode 100644
index 0000000000..6ceb066935
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/bspstarthooks.c
@@ -0,0 +1,533 @@
+/**
+ * @file
+ *
+ * @ingroup lpc24xx
+ *
+ * @brief Startup code.
+ */
+
+/*
+ * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/io.h>
+#include <bsp/start.h>
+#include <bsp/lpc24xx.h>
+#include <bsp/lpc-emc.h>
+#include <bsp/start-config.h>
+
+static BSP_START_TEXT_SECTION void lpc24xx_cpu_delay(unsigned ticks)
+{
+  unsigned i = 0;
+
+  /* One loop execution needs four instructions */
+  ticks /= 4;
+
+  for (i = 0; i <= ticks; ++i) {
+    __asm__ volatile ("nop");
+  }
+}
+
+static BSP_START_TEXT_SECTION void lpc24xx_udelay(unsigned us)
+{
+  lpc24xx_cpu_delay(us * (LPC24XX_CCLK / 1000000));
+}
+
+static BSP_START_TEXT_SECTION void lpc24xx_init_pinsel(void)
+{
+  lpc24xx_pin_config(
+    &lpc24xx_start_config_pinsel [0],
+    LPC24XX_PIN_SET_FUNCTION
+  );
+}
+
+static BSP_START_TEXT_SECTION void lpc24xx_init_emc_static(void)
+{
+  size_t i = 0;
+  size_t chip_count = lpc24xx_start_config_emc_static_chip_count;
+
+  for (i = 0; i < chip_count; ++i) {
+    const lpc24xx_emc_static_chip_config *chip_config =
+      &lpc24xx_start_config_emc_static_chip [i];
+    lpc24xx_emc_static_chip_config chip_config_on_stack;
+    size_t config_size = sizeof(chip_config_on_stack.config);
+
+    bsp_start_memcpy(
+      (int *) &chip_config_on_stack.config,
+      (const int *) &chip_config->config,
+      config_size
+    );
+    bsp_start_memcpy(
+      (int *) chip_config->chip_select,
+      (const int *) &chip_config_on_stack.config,
+      config_size
+    );
+  }
+}
+
+static BSP_START_TEXT_SECTION void lpc24xx_init_emc_dynamic(void)
+{
+  size_t chip_count = lpc24xx_start_config_emc_dynamic_chip_count;
+
+  if (chip_count > 0) {
+    bool do_initialization = true;
+    size_t i = 0;
+
+    for (i = 0; do_initialization && i < chip_count; ++i) {
+      const lpc24xx_emc_dynamic_chip_config *chip_cfg =
+        &lpc24xx_start_config_emc_dynamic_chip [i];
+      volatile lpc_emc_dynamic *chip_select = chip_cfg->chip_select;
+
+      do_initialization = (chip_select->config & EMC_DYN_CFG_B) == 0;
+    }
+
+    if (do_initialization) {
+      volatile lpc_emc *emc = (volatile lpc_emc *) EMC_BASE_ADDR;
+      const lpc24xx_emc_dynamic_config *cfg =
+        &lpc24xx_start_config_emc_dynamic [0];
+      uint32_t dynamiccontrol = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS;
+
+      #ifdef ARM_MULTILIB_ARCH_V7M
+        volatile lpc17xx_scb *scb = &LPC17XX_SCB;
+
+        /* Delay control */
+        scb->emcdlyctl = cfg->emcdlyctl;
+      #endif
+
+      emc->dynamicreadconfig = cfg->readconfig;
+
+      /* Timings */
+      emc->dynamictrp = cfg->trp;
+      emc->dynamictras = cfg->tras;
+      emc->dynamictsrex = cfg->tsrex;
+      emc->dynamictapr = cfg->tapr;
+      emc->dynamictdal = cfg->tdal;
+      emc->dynamictwr = cfg->twr;
+      emc->dynamictrc = cfg->trc;
+      emc->dynamictrfc = cfg->trfc;
+      emc->dynamictxsr = cfg->txsr;
+      emc->dynamictrrd = cfg->trrd;
+      emc->dynamictmrd = cfg->tmrd;
+
+      /* NOP period */
+      emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_NOP;
+      lpc24xx_udelay(200);
+
+      /* Precharge */
+      emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_PALL;
+      emc->dynamicrefresh = 1;
+
+      /*
+       * Perform several refresh cycles with a memory refresh every 16 AHB
+       * clock cycles.  Wait until eight SDRAM refresh cycles have occurred
+       * (128 AHB clock cycles).
+       */
+      lpc24xx_cpu_delay(128);
+
+      /* Refresh timing */
+      emc->dynamicrefresh = cfg->refresh;
+      lpc24xx_cpu_delay(128);
+
+      for (i = 0; i < chip_count; ++i) {
+        const lpc24xx_emc_dynamic_chip_config *chip_cfg =
+          &lpc24xx_start_config_emc_dynamic_chip [i];
+        volatile lpc_emc_dynamic *chip_select = chip_cfg->chip_select;
+        uint32_t config = chip_cfg->config;
+
+        /* Chip select */
+        chip_select->config = config;
+        chip_select->rascas = chip_cfg->rascas;
+
+        /* Set modes */
+        emc->dynamiccontrol = dynamiccontrol | EMC_DYN_CTRL_I_MODE;
+        *(volatile uint32_t *)(chip_cfg->address + chip_cfg->mode);
+
+        /* Enable buffer */
+        chip_select->config = config | EMC_DYN_CFG_B;
+      }
+
+      emc->dynamiccontrol = 0;
+    }
+  }
+}
+
+static BSP_START_TEXT_SECTION void lpc24xx_init_main_oscillator(void)
+{
+  #ifdef ARM_MULTILIB_ARCH_V4
+    if ((SCS & 0x40) == 0) {
+      SCS |= 0x20;
+      while ((SCS & 0x40) == 0) {
+        /* Wait */
+      }
+    }
+  #else
+    volatile lpc17xx_scb *scb = &LPC17XX_SCB;
+
+    if ((scb->scs & LPC17XX_SCB_SCS_OSC_STATUS) == 0) {
+      scb->scs |= LPC17XX_SCB_SCS_OSC_ENABLE;
+      while ((scb->scs & LPC17XX_SCB_SCS_OSC_STATUS) == 0) {
+        /* Wait */
+      }
+    }
+  #endif
+}
+
+#ifdef ARM_MULTILIB_ARCH_V4
+
+static BSP_START_TEXT_SECTION void lpc24xx_pll_config(
+  uint32_t val
+)
+{
+  PLLCON = val;
+  PLLFEED = 0xaa;
+  PLLFEED = 0x55;
+}
+
+/**
+ * @brief Sets the Phase Locked Loop (PLL).
+ *
+ * All parameter values are the actual register field values.
+ *
+ * @param clksrc Selects the clock source for the PLL.
+ *
+ * @param nsel Selects PLL pre-divider value (sometimes named psel).
+ *
+ * @param msel Selects PLL multiplier value.
+ *
+ * @param cclksel Selects the divide value for creating the CPU clock (CCLK)
+ * from the PLL output.
+ */
+static BSP_START_TEXT_SECTION void lpc24xx_set_pll(
+  unsigned clksrc,
+  unsigned nsel,
+  unsigned msel,
+  unsigned cclksel
+)
+{
+  uint32_t pllstat = PLLSTAT;
+  uint32_t pllcfg = SET_PLLCFG_NSEL(0, nsel) | SET_PLLCFG_MSEL(0, msel);
+  uint32_t clksrcsel = SET_CLKSRCSEL_CLKSRC(0, clksrc);
+  uint32_t cclkcfg = SET_CCLKCFG_CCLKSEL(0, cclksel | 1);
+  bool pll_enabled = (pllstat & PLLSTAT_PLLE) != 0;
+
+  /* Disconnect PLL if necessary */
+  if ((pllstat & PLLSTAT_PLLC) != 0) {
+    if (pll_enabled) {
+      /* Check if we run already with the desired settings */
+      if (PLLCFG == pllcfg && CLKSRCSEL == clksrcsel && CCLKCFG == cclkcfg) {
+        /* Nothing to do */
+        return;
+      }
+      lpc24xx_pll_config(PLLCON_PLLE);
+    } else {
+      lpc24xx_pll_config(0);
+    }
+  }
+
+  /* Set CPU clock divider to a reasonable save value */
+  CCLKCFG = 0;
+
+  /* Disable PLL if necessary */
+  if (pll_enabled) {
+    lpc24xx_pll_config(0);
+  }
+
+  /* Select clock source */
+  CLKSRCSEL = clksrcsel;
+
+  /* Set PLL Configuration Register */
+  PLLCFG = pllcfg;
+
+  /* Enable PLL */
+  lpc24xx_pll_config(PLLCON_PLLE);
+
+  /* Wait for lock */
+  while ((PLLSTAT & PLLSTAT_PLOCK) == 0) {
+    /* Wait */
+  }
+
+  /* Set CPU clock divider and ensure that we have an odd value */
+  CCLKCFG = cclkcfg;
+
+  /* Connect PLL */
+  lpc24xx_pll_config(PLLCON_PLLE | PLLCON_PLLC);
+}
+
+#else /* ARM_MULTILIB_ARCH_V4 */
+
+static BSP_START_TEXT_SECTION void lpc17xx_pll_config(
+  volatile lpc17xx_pll *pll,
+  uint32_t val
+)
+{
+  pll->con = val;
+  pll->feed = 0xaa;
+  pll->feed = 0x55;
+}
+
+static BSP_START_TEXT_SECTION void lpc17xx_set_pll(
+  unsigned msel,
+  unsigned psel,
+  unsigned cclkdiv
+)
+{
+  volatile lpc17xx_scb *scb = &LPC17XX_SCB;
+  volatile lpc17xx_pll *pll = &scb->pll_0;
+  uint32_t pllcfg = LPC17XX_PLL_SEL_MSEL(msel)
+    | LPC17XX_PLL_SEL_PSEL(psel);
+  uint32_t pllstat = LPC17XX_PLL_STAT_PLLE
+    | LPC17XX_PLL_STAT_PLOCK | pllcfg;
+  uint32_t cclksel_cclkdiv = LPC17XX_SCB_CCLKSEL_CCLKDIV(cclkdiv);
+  uint32_t cclksel = LPC17XX_SCB_CCLKSEL_CCLKSEL | cclksel_cclkdiv;
+
+  if (
+    pll->stat != pllstat
+      || scb->cclksel != cclksel
+      || scb->clksrcsel != LPC17XX_SCB_CLKSRCSEL_CLKSRC
+  ) {
+    /* Use SYSCLK for CCLK */
+    scb->cclksel = LPC17XX_SCB_CCLKSEL_CCLKDIV(1);
+
+    /* Turn off USB */
+    scb->usbclksel = 0;
+
+    /* Disable PLL */
+    lpc17xx_pll_config(pll, 0);
+
+    /* Select main oscillator as clock source */
+    scb->clksrcsel = LPC17XX_SCB_CLKSRCSEL_CLKSRC;
+
+    /* Set PLL configuration */
+    pll->cfg = pllcfg;
+
+    /* Set the CCLK, PCLK and EMCCLK divider */
+    scb->cclksel = cclksel_cclkdiv;
+    scb->pclksel = LPC17XX_SCB_PCLKSEL_PCLKDIV(cclkdiv * LPC24XX_PCLKDIV);
+    scb->emcclksel = LPC24XX_EMCCLKDIV == 1 ? 0 : LPC17XX_SCB_EMCCLKSEL_EMCDIV;
+
+    /* Enable PLL */
+    lpc17xx_pll_config(pll, LPC17XX_PLL_CON_PLLE);
+
+    /* Wait for lock */
+    while ((pll->stat & LPC17XX_PLL_STAT_PLOCK) == 0) {
+      /* Wait */
+    }
+
+    /* Use the PLL clock */
+    scb->cclksel = cclksel;
+  }
+}
+
+#endif /* ARM_MULTILIB_ARCH_V4 */
+
+static BSP_START_TEXT_SECTION void lpc24xx_init_pll(void)
+{
+  #ifdef ARM_MULTILIB_ARCH_V4
+    #if LPC24XX_OSCILLATOR_MAIN == 12000000U
+      #if LPC24XX_CCLK == 72000000U
+        lpc24xx_set_pll(1, 0, 11, 3);
+      #elif LPC24XX_CCLK == 51612800U
+        lpc24xx_set_pll(1, 30, 399, 5);
+      #else
+        #error "unexpected CCLK"
+      #endif
+    #elif LPC24XX_OSCILLATOR_MAIN == 3686400U
+      #if LPC24XX_CCLK == 58982400U
+        lpc24xx_set_pll(1, 0, 47, 5);
+      #else
+        #error "unexpected CCLK"
+      #endif
+    #else
+      #error "unexpected main oscillator frequency"
+    #endif
+  #else
+    #if LPC24XX_OSCILLATOR_MAIN == 12000000U
+      #if LPC24XX_CCLK == 120000000U
+        lpc17xx_set_pll(9, 0, 1);
+      #elif LPC24XX_CCLK == 96000000U
+        lpc17xx_set_pll(7, 0, 1);
+      #elif LPC24XX_CCLK == 72000000U
+        lpc17xx_set_pll(5, 1, 1);
+      #elif LPC24XX_CCLK == 48000000U
+        lpc17xx_set_pll(3, 1, 1);
+      #else
+        #error "unexpected CCLK"
+      #endif
+    #else
+      #error "unexpected main oscillator frequency"
+    #endif
+  #endif
+}
+
+static BSP_START_TEXT_SECTION void lpc24xx_init_memory_map(void)
+{
+  #ifdef ARM_MULTILIB_ARCH_V4
+    /* Re-map interrupt vectors to internal RAM */
+    MEMMAP = SET_MEMMAP_MAP(MEMMAP, 2);
+  #else
+    volatile lpc17xx_scb *scb = &LPC17XX_SCB;
+
+    scb->memmap = LPC17XX_SCB_MEMMAP_MAP;
+  #endif
+
+  /* Use normal memory map */
+  EMC_CTRL &= ~0x2U;
+}
+
+static BSP_START_TEXT_SECTION void lpc24xx_init_memory_accelerator(void)
+{
+  #ifdef ARM_MULTILIB_ARCH_V4
+    /* Fully enable memory accelerator module functions (MAM) */
+    MAMCR = 0;
+    #if LPC24XX_CCLK <= 20000000U
+      MAMTIM = 0x1;
+    #elif LPC24XX_CCLK <= 40000000U
+      MAMTIM = 0x2;
+    #elif LPC24XX_CCLK <= 60000000U
+      MAMTIM = 0x3;
+    #else
+      MAMTIM = 0x4;
+    #endif
+    MAMCR = 0x2;
+
+    /* Enable fast IO for ports 0 and 1 */
+    SCS |= 0x1;
+  #else
+    volatile lpc17xx_scb *scb = &LPC17XX_SCB;
+
+    #if LPC24XX_CCLK <= 20000000U
+      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x0);
+    #elif LPC24XX_CCLK <= 40000000U
+      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x1);
+    #elif LPC24XX_CCLK <= 60000000U
+      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x2);
+    #elif LPC24XX_CCLK <= 80000000U
+      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x3);
+    #elif LPC24XX_CCLK <= 100000000U
+      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x4);
+    #else
+      scb->flashcfg = LPC17XX_SCB_FLASHCFG_FLASHTIM(0x5);
+    #endif
+  #endif
+}
+
+static BSP_START_TEXT_SECTION void lpc24xx_stop_gpdma(void)
+{
+  #ifdef LPC24XX_STOP_GPDMA
+    #ifdef ARM_MULTILIB_ARCH_V4
+      bool has_power = (PCONP & PCONP_GPDMA) != 0;
+    #else
+      volatile lpc17xx_scb *scb = &LPC17XX_SCB;
+      bool has_power = (scb->pconp & LPC17XX_SCB_PCONP_GPDMA) != 0;
+    #endif
+
+    if (has_power) {
+      GPDMA_CONFIG = 0;
+
+      #ifdef ARM_MULTILIB_ARCH_V4
+        PCONP &= ~PCONP_GPDMA;
+      #else
+        scb->pconp &= ~LPC17XX_SCB_PCONP_GPDMA;
+      #endif
+    }
+  #endif
+}
+
+static BSP_START_TEXT_SECTION void lpc24xx_stop_ethernet(void)
+{
+  #ifdef LPC24XX_STOP_ETHERNET
+    #ifdef ARM_MULTILIB_ARCH_V4
+      bool has_power = (PCONP & PCONP_ETHERNET) != 0;
+    #else
+      volatile lpc17xx_scb *scb = &LPC17XX_SCB;
+      bool has_power = (scb->pconp & LPC17XX_SCB_PCONP_ENET) != 0;
+    #endif
+
+    if (has_power) {
+      MAC_COMMAND = 0x38;
+      MAC_MAC1 = 0xcf00;
+      MAC_MAC1 = 0;
+
+      #ifdef ARM_MULTILIB_ARCH_V4
+        PCONP &= ~PCONP_ETHERNET;
+      #else
+        scb->pconp &= ~LPC17XX_SCB_PCONP_ENET;
+      #endif
+    }
+  #endif
+}
+
+static BSP_START_TEXT_SECTION void lpc24xx_stop_usb(void)
+{
+  #ifdef LPC24XX_STOP_USB
+    #ifdef ARM_MULTILIB_ARCH_V4
+      bool has_power = (PCONP & PCONP_USB) != 0;
+    #else
+      volatile lpc17xx_scb *scb = &LPC17XX_SCB;
+      bool has_power = (scb->pconp & LPC17XX_SCB_PCONP_USB) != 0;
+    #endif
+
+    if (has_power) {
+      OTG_CLK_CTRL = 0;
+
+      #ifdef ARM_MULTILIB_ARCH_V4
+        PCONP &= ~PCONP_USB;
+      #else
+        scb->pconp &= ~LPC17XX_SCB_PCONP_USB;
+        scb->usbclksel = 0;
+      #endif
+    }
+  #endif
+}
+
+static BSP_START_TEXT_SECTION void lpc24xx_init_mpu(void)
+{
+  #ifdef ARM_MULTILIB_ARCH_V7M
+    volatile ARMV7M_MPU *mpu = _ARMV7M_MPU;
+    size_t region_count = lpc24xx_start_config_mpu_region_count;
+    size_t i = 0;
+
+    for (i = 0; i < region_count; ++i) {
+      mpu->rbar = lpc24xx_start_config_mpu_region [i].rbar;
+      mpu->rasr = lpc24xx_start_config_mpu_region [i].rasr;
+    }
+
+    if (region_count > 0) {
+      mpu->ctrl = ARMV7M_MPU_CTRL_ENABLE;
+    }
+  #endif
+}
+
+BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
+{
+  lpc24xx_init_main_oscillator();
+  lpc24xx_init_pll();
+  lpc24xx_init_pinsel();
+  lpc24xx_init_emc_static();
+}
+
+BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
+{
+  lpc24xx_init_memory_map();
+  lpc24xx_init_memory_accelerator();
+  lpc24xx_init_emc_dynamic();
+  lpc24xx_init_mpu();
+  lpc24xx_stop_gpdma();
+  lpc24xx_stop_ethernet();
+  lpc24xx_stop_usb();
+  bsp_start_copy_sections();
+  bsp_start_clear_bss();
+
+  /* At this point we can use objects outside the .start section */
+}
diff --git a/bsps/arm/lpc24xx/start/fb-config.c b/bsps/arm/lpc24xx/start/fb-config.c
new file mode 100644
index 0000000000..d1fa33c95a
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/fb-config.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp/arm-pl111-fb.h>
+
+#include <bsp.h>
+#include <bsp/fatal.h>
+#include <bsp/io.h>
+#include <bsp/lcd.h>
+#include <bsp/lpc24xx.h>
+
+static const lpc24xx_pin_range tft_16_bit_5_6_5_pins[] = {
+  LPC24XX_PIN_LCD_DCLK,
+  LPC24XX_PIN_LCD_FP,
+  LPC24XX_PIN_LCD_LP,
+  LPC24XX_PIN_LCD_VD_3_P4_29,
+  LPC24XX_PIN_LCD_VD_4_P2_6,
+  LPC24XX_PIN_LCD_VD_5_P2_7,
+  LPC24XX_PIN_LCD_VD_6_P2_8,
+  LPC24XX_PIN_LCD_VD_7_P2_9,
+  LPC24XX_PIN_LCD_VD_10_P1_20,
+  LPC24XX_PIN_LCD_VD_11_P1_21,
+  LPC24XX_PIN_LCD_VD_12_P1_22,
+  LPC24XX_PIN_LCD_VD_13_P1_23,
+  LPC24XX_PIN_LCD_VD_14_P1_24,
+  LPC24XX_PIN_LCD_VD_15_P1_25,
+  LPC24XX_PIN_LCD_VD_19_P2_13,
+  LPC24XX_PIN_LCD_VD_20_P1_26,
+  LPC24XX_PIN_LCD_VD_21_P1_27,
+  LPC24XX_PIN_LCD_VD_22_P1_28,
+  LPC24XX_PIN_LCD_VD_23_P1_29,
+  LPC24XX_PIN_TERMINAL
+};
+
+static void fb_set_up(const pl111_fb_config *cfg)
+{
+  rtems_status_code sc;
+
+  sc = lpc24xx_module_enable(LPC24XX_MODULE_LCD, LPC24XX_MODULE_PCLK_DEFAULT);
+  if (sc != RTEMS_SUCCESSFUL) {
+    bsp_fatal(LPC24XX_FATAL_PL111_SET_UP);
+  }
+
+  #ifdef ARM_MULTILIB_ARCH_V4
+    PINSEL11 = BSP_FLD32(LCD_MODE_TFT_16_BIT_5_6_5, 1, 3) | BSP_BIT32(0);
+  #endif
+
+  #ifdef ARM_MULTILIB_ARCH_V7M
+    volatile lpc17xx_scb *scb = &LPC17XX_SCB;
+
+    scb->matrixarb = 0x0c09;
+  #endif
+}
+
+static void fb_pins_set_up(const pl111_fb_config *cfg)
+{
+  rtems_status_code sc;
+
+  sc = lpc24xx_pin_config(tft_16_bit_5_6_5_pins, LPC24XX_PIN_SET_FUNCTION);
+  if (sc != RTEMS_SUCCESSFUL) {
+    bsp_fatal(LPC24XX_FATAL_PL111_PINS_SET_UP);
+  }
+}
+
+static void fb_pins_tear_down(const pl111_fb_config *cfg)
+{
+  rtems_status_code sc;
+
+  sc = lpc24xx_pin_config(tft_16_bit_5_6_5_pins, LPC24XX_PIN_SET_INPUT);
+  if (sc != RTEMS_SUCCESSFUL) {
+    bsp_fatal(LPC24XX_FATAL_PL111_PINS_TEAR_DOWN);
+  }
+}
+
+static void fb_tear_down(const pl111_fb_config *cfg)
+{
+  rtems_status_code sc;
+
+  #ifdef ARM_MULTILIB_ARCH_V4
+    PINSEL11 = 0;
+  #endif
+
+  sc = lpc24xx_module_disable(LPC24XX_MODULE_LCD);
+  if (sc != RTEMS_SUCCESSFUL) {
+    bsp_fatal(LPC24XX_FATAL_PL111_TEAR_DOWN);
+  }
+}
+
+static const pl111_fb_config fb_config = {
+  .regs = (volatile pl111 *) LCD_BASE_ADDR,
+
+  .timing0 = PL111_LCD_TIMING0_PPL(640 / 16 - 1)
+    | PL111_LCD_TIMING0_HSW(0x1d)
+    | PL111_LCD_TIMING0_HFP(0x0f)
+    | PL111_LCD_TIMING0_HBP(0x71),
+  .timing1 = PL111_LCD_TIMING1_LPP(480 - 1)
+    | PL111_LCD_TIMING1_VSW(0x02)
+    | PL111_LCD_TIMING1_VFP(0x0a)
+    | PL111_LCD_TIMING1_VBP(0x20),
+  .timing2 = PL111_LCD_TIMING2_PCD_LO(0x3)
+    | PL111_LCD_TIMING2_ACB(0x0)
+    | PL111_LCD_TIMING2_IVS
+    | PL111_LCD_TIMING2_IHS
+    | PL111_LCD_TIMING2_IPC
+    | PL111_LCD_TIMING2_CPL(640 - 1)
+    | PL111_LCD_TIMING2_PCD_HI(0x0),
+  .timing3 = 0x0,
+  .control = PL111_LCD_CONTROL_LCD_TFT
+    | PL111_LCD_CONTROL_LCD_BPP(PL111_LCD_CONTROL_LCD_BPP_16)
+    | PL111_LCD_CONTROL_BGR,
+  .power_delay_in_us = 100000,
+
+  .set_up = fb_set_up,
+  .pins_set_up = fb_pins_set_up,
+  .pins_tear_down = fb_pins_tear_down,
+  .tear_down = fb_tear_down
+};
+
+const pl111_fb_config *arm_pl111_fb_get_config(void)
+{
+  return &fb_config;
+}
diff --git a/bsps/arm/lpc24xx/start/linkcmds.lpc17xx_ea_ram b/bsps/arm/lpc24xx/start/linkcmds.lpc17xx_ea_ram
new file mode 100644
index 0000000000..d98626108d
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/linkcmds.lpc17xx_ea_ram
@@ -0,0 +1,27 @@
+/* LPC1788 OEM Board from Embedded Artists */
+
+MEMORY {
+	RAM_INT (AIW) : ORIGIN = 0x10000000, LENGTH = 64k
+	RAM_PER (AIW) : ORIGIN = 0x20000000, LENGTH = 32k
+	RAM_EXT (AIW) : ORIGIN = 0xa0000000, LENGTH = 32M
+}
+
+REGION_ALIAS ("REGION_START", RAM_EXT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", RAM_EXT);
+REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_INT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_INT);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_INT);
+REGION_ALIAS ("REGION_BSS", RAM_EXT);
+REGION_ALIAS ("REGION_WORK", RAM_EXT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT);
+
+INCLUDE linkcmds.armv7m
diff --git a/bsps/arm/lpc24xx/start/linkcmds.lpc17xx_ea_rom_int b/bsps/arm/lpc24xx/start/linkcmds.lpc17xx_ea_rom_int
new file mode 100644
index 0000000000..db8c27f37f
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/linkcmds.lpc17xx_ea_rom_int
@@ -0,0 +1,27 @@
+/* LPC1788 OEM Board from Embedded Artists */
+
+MEMORY {
+	ROM_INT (RX)  : ORIGIN = 0x00000000, LENGTH = 512k
+	RAM_INT (AIW) : ORIGIN = 0x10000000, LENGTH = 64k
+	RAM_EXT (AIW) : ORIGIN = 0xa0000000, LENGTH = 32M
+}
+
+REGION_ALIAS ("REGION_START", ROM_INT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", ROM_INT);
+REGION_ALIAS ("REGION_TEXT_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_RODATA", ROM_INT);
+REGION_ALIAS ("REGION_RODATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_DATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_INT);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_BSS", RAM_EXT);
+REGION_ALIAS ("REGION_WORK", RAM_EXT);
+REGION_ALIAS ("REGION_STACK", RAM_EXT);
+REGION_ALIAS ("REGION_NOCACHE", RAM_EXT);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_EXT);
+
+INCLUDE linkcmds.armv7m
diff --git a/bsps/arm/lpc24xx/start/linkcmds.lpc17xx_plx800_ram b/bsps/arm/lpc24xx/start/linkcmds.lpc17xx_plx800_ram
new file mode 100644
index 0000000000..e507877a84
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/linkcmds.lpc17xx_plx800_ram
@@ -0,0 +1,33 @@
+/**
+ * @file
+ *
+ * @brief Memory map for PLX800 (LPC1778).
+ */
+
+MEMORY {
+	ROM_INT : ORIGIN = 0x00000000, LENGTH = 512k
+	RAM_INT : ORIGIN = 0x10000000, LENGTH = 64k
+	RAM_PER : ORIGIN = 0x20000000, LENGTH = 32k
+	ROM_EXT : ORIGIN = 0x80000000, LENGTH = 4M
+	RAM_EXT : ORIGIN = 0xa0000000, LENGTH = 32M
+}
+
+REGION_ALIAS ("REGION_START", RAM_EXT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", RAM_EXT);
+REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_INT);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_BSS", RAM_EXT);
+REGION_ALIAS ("REGION_WORK", RAM_EXT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT);
+
+INCLUDE linkcmds.armv7m
diff --git a/bsps/arm/lpc24xx/start/linkcmds.lpc17xx_plx800_rom_int b/bsps/arm/lpc24xx/start/linkcmds.lpc17xx_plx800_rom_int
new file mode 100644
index 0000000000..2ae0a58840
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/linkcmds.lpc17xx_plx800_rom_int
@@ -0,0 +1,33 @@
+/**
+ * @file
+ *
+ * @brief Memory map for PLX800 (LPC1778).
+ */
+
+MEMORY {
+	ROM_INT : ORIGIN = 0x00000000, LENGTH = 512k
+	RAM_INT : ORIGIN = 0x10000000, LENGTH = 64k
+	RAM_PER : ORIGIN = 0x20000000, LENGTH = 32k
+	ROM_EXT : ORIGIN = 0x80000000, LENGTH = 4M
+	RAM_EXT : ORIGIN = 0xa0000000, LENGTH = 32M
+}
+
+REGION_ALIAS ("REGION_START", ROM_INT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", ROM_INT);
+REGION_ALIAS ("REGION_TEXT_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_RODATA", ROM_INT);
+REGION_ALIAS ("REGION_RODATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_DATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_INT);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_BSS", RAM_EXT);
+REGION_ALIAS ("REGION_WORK", RAM_EXT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT);
+
+INCLUDE linkcmds.armv7m
diff --git a/bsps/arm/lpc24xx/start/linkcmds.lpc2362 b/bsps/arm/lpc24xx/start/linkcmds.lpc2362
new file mode 100644
index 0000000000..e5bae18075
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/linkcmds.lpc2362
@@ -0,0 +1,70 @@
+/**
+ * @file
+ *
+ * @ingroup lpc24xx_linker_lpc2362
+ *
+ * @brief Memory map.
+ */
+
+/**
+ * @defgroup lpc24xx_linker_lpc2362 LPC2362 Memory Map
+ *
+ * @ingroup bsp_linker
+ *
+ * @brief LPC2362 memory map.
+ *
+ * <table>
+ *   <tr><th>Region Name</th><th>Region Begin</th><th>Region Size</th></tr>
+ *   <tr><td>RAM_INT</td><td>0x40000000</td><td>32k</td></tr>
+ *   <tr><td>RAM_USB</td><td>0x7fd00000</td><td>8k</td></tr>
+ *   <tr><td>RAM_ETH</td><td>0x7fe00000</td><td>16k</td></tr>
+ *   <tr><td>ROM_INT</td><td>0x00000000</td><td>128k</td></tr>
+ * </table>
+ *
+ * <table>
+ *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
+ *   <tr><td>.start</td><td>ROM_INT</td><td></td></tr>
+ *   <tr><td>.text</td><td>ROM_INT</td><td>ROM_INT</td></tr>
+ *   <tr><td>.rodata</td><td>ROM_INT</td><td>ROM_INT</td></tr>
+ *   <tr><td>.data</td><td>RAM_INT</td><td>ROM_INT</td></tr>
+ *   <tr><td>.fast</td><td>RAM_INT</td><td>ROM_INT</td></tr>
+ *   <tr><td>.bss</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.work</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.stack</td><td>RAM_INT</td><td></td></tr>
+ * </table>
+ */
+
+MEMORY {
+	RAM_INT (AIW) : ORIGIN = 0x40000000, LENGTH = 32k
+	RAM_USB (AIW) : ORIGIN = 0x7fd00000, LENGTH = 8k
+	RAM_ETH (AIW) : ORIGIN = 0x7fe00000, LENGTH = 16k
+	ROM_INT (RX)  : ORIGIN = 0x00000000, LENGTH = 128k
+}
+
+REGION_ALIAS ("REGION_START", ROM_INT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", ROM_INT);
+REGION_ALIAS ("REGION_TEXT_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_RODATA", ROM_INT);
+REGION_ALIAS ("REGION_RODATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_DATA", RAM_INT);
+REGION_ALIAS ("REGION_DATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_INT);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_BSS", RAM_INT);
+REGION_ALIAS ("REGION_WORK", RAM_INT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT);
+
+lpc24xx_region_heap_0_begin = ORIGIN (RAM_ETH);
+lpc24xx_region_heap_0_size = LENGTH (RAM_ETH);
+lpc24xx_region_heap_0_end = lpc24xx_region_heap_0_begin + lpc24xx_region_heap_0_size;
+
+lpc24xx_region_heap_1_begin = ORIGIN (RAM_USB);
+lpc24xx_region_heap_1_size = LENGTH (RAM_USB);
+lpc24xx_region_heap_1_end = lpc24xx_region_heap_1_begin + lpc24xx_region_heap_1_size;
+
+INCLUDE linkcmds.armv4
diff --git a/bsps/arm/lpc24xx/start/linkcmds.lpc23xx_tli800 b/bsps/arm/lpc24xx/start/linkcmds.lpc23xx_tli800
new file mode 100644
index 0000000000..697b040a84
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/linkcmds.lpc23xx_tli800
@@ -0,0 +1,74 @@
+/**
+ * @file
+ *
+ * @ingroup lpc24xx_linker_lpc23xx_tli800
+ *
+ * @brief Memory map.
+ */
+
+/**
+ * @defgroup lpc24xx_linker_lpc23xx_tli800 TLI800 Memory Map
+ *
+ * @ingroup bsp_linker
+ *
+ * @brief TLI800 memory map.
+ *
+ * <table>
+ *   <tr><th>Region Name</th><th>Region Begin</th><th>Region Size</th></tr>
+ *   <tr><td>RAM_INT</td><td>0x40000000</td><td>32k</td></tr>
+ *   <tr><td>RAM_USB</td><td>0x7fd00000</td><td>8k</td></tr>
+ *   <tr><td>RAM_ETH</td><td>0x7fe00000</td><td>16k</td></tr>
+ *   <tr><td>ROM_BOOT</td><td>0x00000000</td><td>4k</td></tr>
+ *   <tr><td>ROM_CFG</td><td>0x00001000</td><td>4k</td></tr>
+ *   <tr><td>ROM_INT</td><td>0x00002000</td><td>120k</td></tr>
+ * </table>
+ *
+ * <table>
+ *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
+ *   <tr><td>.start</td><td>ROM_BOOT</td><td></td></tr>
+ *   <tr><td>.text</td><td>ROM_INT</td><td>ROM_INT</td></tr>
+ *   <tr><td>.rodata</td><td>ROM_INT</td><td>ROM_INT</td></tr>
+ *   <tr><td>.data</td><td>RAM_INT</td><td>ROM_INT</td></tr>
+ *   <tr><td>.fast</td><td>RAM_INT</td><td>ROM_INT</td></tr>
+ *   <tr><td>.bss</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.work</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.stack</td><td>RAM_INT</td><td></td></tr>
+ * </table>
+ */
+
+MEMORY {
+	RAM_INT (AIW) : ORIGIN = 0x40000000, LENGTH = 32k
+	RAM_USB (AIW) : ORIGIN = 0x7fd00000, LENGTH = 8k
+	RAM_ETH (AIW) : ORIGIN = 0x7fe00000, LENGTH = 16k
+	ROM_BOOT (RX) : ORIGIN = 0x00000000, LENGTH = 4k
+	ROM_CFG (RX)  : ORIGIN = 0x00001000, LENGTH = 4k
+	ROM_INT (RX)  : ORIGIN = 0x00002000, LENGTH = 120k
+}
+
+REGION_ALIAS ("REGION_START", ROM_BOOT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", ROM_INT);
+REGION_ALIAS ("REGION_TEXT_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_RODATA", ROM_INT);
+REGION_ALIAS ("REGION_RODATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_DATA", RAM_INT);
+REGION_ALIAS ("REGION_DATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_INT);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_BSS", RAM_INT);
+REGION_ALIAS ("REGION_WORK", RAM_INT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT);
+
+lpc24xx_region_heap_0_begin = ORIGIN (RAM_ETH);
+lpc24xx_region_heap_0_size = LENGTH (RAM_ETH);
+lpc24xx_region_heap_0_end = lpc24xx_region_heap_0_begin + lpc24xx_region_heap_0_size;
+
+lpc24xx_region_heap_1_begin = ORIGIN (RAM_USB);
+lpc24xx_region_heap_1_size = LENGTH (RAM_USB);
+lpc24xx_region_heap_1_end = lpc24xx_region_heap_1_begin + lpc24xx_region_heap_1_size;
+
+INCLUDE linkcmds.armv4
diff --git a/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_ea b/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_ea
new file mode 100644
index 0000000000..80b1e13187
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_ea
@@ -0,0 +1,59 @@
+/**
+ * @file
+ *
+ * @ingroup lpc24xx_linker_ea
+ *
+ * @brief Memory map.
+ */
+
+/**
+ * @defgroup lpc24xx_linker_ea QVGA Base Board Memory Map
+ *
+ * @ingroup bsp_linker
+ *
+ * @brief QVGA Base Board from Embedded Artists (LPC2478) memory map.
+ *
+ * <table>
+ *   <tr><th>Region Name</th><th>Region Begin</th><th>Region Size</th></tr>
+ *   <tr><td>RAM_INT</td><td>0x40000000</td><td>64k</td></tr>
+ *   <tr><td>RAM_EXT</td><td>0xa0000000</td><td>32M</td></tr>
+ * </table>
+ *
+ * <table>
+ *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
+ *   <tr><td>.start</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.vector</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.text</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.rodata</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.data</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.fast</td><td>RAM_INT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.bss</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.work</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.stack</td><td>RAM_INT</td><td></td></tr>
+ * </table>
+ */
+
+MEMORY {
+	RAM_INT (AIW) : ORIGIN = 0x40000000, LENGTH = 64k
+	RAM_EXT (AIW) : ORIGIN = 0xa0000000, LENGTH = 32M
+}
+
+REGION_ALIAS ("REGION_START", RAM_EXT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", RAM_EXT);
+REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_INT);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_BSS", RAM_EXT);
+REGION_ALIAS ("REGION_WORK", RAM_EXT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT);
+
+INCLUDE linkcmds.armv4
diff --git a/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_ncs_ram b/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_ncs_ram
new file mode 100644
index 0000000000..9f421f3555
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_ncs_ram
@@ -0,0 +1,60 @@
+/**
+ * @file
+ *
+ * @ingroup lpc24xx_linker_ncs_ram
+ *
+ * @brief Memory map.
+ */
+
+/**
+ * @defgroup lpc24xx_linker_ncs_ram NCS Application Memory Map
+ *
+ * @ingroup bsp_linker
+ *
+ * @brief NCS application memory map.
+ *
+ * <table>
+ *   <tr><th>Region Name</th><th>Region Begin</th><th>Region Size</th></tr>
+ *   <tr><td>RAM_INT</td><td>0x40000000</td><td>64k</td></tr>
+ *   <tr><td>RAM_EXT</td><td>0xa0000000</td><td>8M</td></tr>
+ * </table>
+ *
+ * <table>
+ *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
+ *   <tr><td>.start</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.vector</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.text</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.rodata</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.data</td><td>RAM_EXT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.fast</td><td>RAM_INT</td><td>RAM_EXT</td></tr>
+ *   <tr><td>.bss</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.work</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.stack</td><td>RAM_INT</td><td></td></tr>
+ * </table>
+ */
+
+MEMORY {
+	RAM_INT (AIW) : ORIGIN = 0x40000000, LENGTH = 64k
+	RAM_USB (AIW) : ORIGIN = 0x7fd00000, LENGTH = 16k
+	RAM_EXT (AIW) : ORIGIN = 0xa0000000, LENGTH = 8M
+}
+
+REGION_ALIAS ("REGION_START", RAM_EXT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", RAM_EXT);
+REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_USB);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_BSS", RAM_EXT);
+REGION_ALIAS ("REGION_WORK", RAM_EXT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT);
+
+INCLUDE linkcmds.armv4
diff --git a/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_ncs_rom_ext b/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_ncs_rom_ext
new file mode 100644
index 0000000000..7618a342bd
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_ncs_rom_ext
@@ -0,0 +1,64 @@
+/**
+ * @file
+ *
+ * @ingroup lpc24xx_linker_ncs_rom_ext
+ *
+ * @brief Memory map.
+ */
+
+/**
+ * @defgroup lpc24xx_linker_ncs_rom_ext NCS Bootloader (LPC2470) Memory Map
+ *
+ * @ingroup bsp_linker
+ *
+ * @brief NCS bootloader (LPC2470) memory map.
+ *
+ * <table>
+ *   <tr><th>Region Name</th><th>Region Begin</th><th>Region Size</th></tr>
+ *   <tr><td>RAM_INT</td><td>0x40000000</td><td>64k</td></tr>
+ *   <tr><td>RAM_EXT</td><td>0xa0400000</td><td>4M</td></tr>
+ *   <tr><td>ROM_BOOT</td><td>0x81000000</td><td>16k</td></tr>
+ *   <tr><td>ROM_EXT</td><td>0x81010000</td><td>2M - 64k</td></tr>
+ * </table>
+ *
+ * <table>
+ *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
+ *   <tr><td>.start</td><td>ROM_BOOT</td><td></td></tr>
+ *   <tr><td>.vector</td><td>RAM_INT</td><td></td></tr>
+ *   <tr><td>.text</td><td>RAM_EXT</td><td>ROM_EXT</td></tr>
+ *   <tr><td>.rodata</td><td>RAM_EXT</td><td>ROM_EXT</td></tr>
+ *   <tr><td>.data</td><td>RAM_EXT</td><td>ROM_EXT</td></tr>
+ *   <tr><td>.fast</td><td>RAM_INT</td><td>ROM_BOOT</td></tr>
+ *   <tr><td>.bss</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.work</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.stack</td><td>RAM_INT</td><td></td></tr>
+ * </table>
+ */
+
+MEMORY {
+	RAM_INT (AIW) : ORIGIN = 0x40000000, LENGTH = 64k
+	RAM_USB (AIW) : ORIGIN = 0x7fd00000, LENGTH = 16k
+	RAM_EXT (AIW) : ORIGIN = 0xa0400000, LENGTH = 4M
+	ROM_BOOT (RX) : ORIGIN = 0x81000000, LENGTH = 16k
+	ROM_EXT (RX)  : ORIGIN = 0x81010000, LENGTH = 2M - 64k
+}
+
+REGION_ALIAS ("REGION_START", ROM_BOOT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", RAM_EXT);
+REGION_ALIAS ("REGION_TEXT_LOAD", ROM_EXT);
+REGION_ALIAS ("REGION_RODATA", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA_LOAD", ROM_EXT);
+REGION_ALIAS ("REGION_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_DATA_LOAD", ROM_EXT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM_BOOT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_USB);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM_BOOT);
+REGION_ALIAS ("REGION_BSS", RAM_EXT);
+REGION_ALIAS ("REGION_WORK", RAM_EXT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT);
+
+INCLUDE linkcmds.armv4
diff --git a/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_ncs_rom_int b/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_ncs_rom_int
new file mode 100644
index 0000000000..47b79e7b5c
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_ncs_rom_int
@@ -0,0 +1,64 @@
+/**
+ * @file
+ *
+ * @ingroup lpc24xx_linker_ncs_rom_int
+ *
+ * @brief Memory map.
+ */
+
+/**
+ * @defgroup lpc24xx_linker_ncs_rom_int NCS Bootloader (LPC2478) Memory Map
+ *
+ * @ingroup bsp_linker
+ *
+ * @brief NCS bootloader (LPC2478) memory map.
+ *
+ * <table>
+ *   <tr><th>Region Name</th><th>Region Begin</th><th>Region Size</th></tr>
+ *   <tr><td>RAM_VEC</td><td>0x40000000</td><td>32k</td></tr>
+ *   <tr><td>RAM_INT</td><td>0x40008000</td><td>32k</td></tr>
+ *   <tr><td>RAM_EXT</td><td>0xa0400000</td><td>4M</td></tr>
+ *   <tr><td>ROM_INT</td><td>0x00000000</td><td>512k - 8k</td></tr>
+ * </table>
+ *
+ * <table>
+ *   <tr><th>Section Name</th><th>Section Runtime Region</th><th>Section Load Region</th></tr>
+ *   <tr><td>.start</td><td>ROM_INT</td><td></td></tr>
+ *   <tr><td>.vector</td><td>RAM_VEC</td><td></td></tr>
+ *   <tr><td>.text</td><td>ROM_INT</td><td>ROM_INT</td></tr>
+ *   <tr><td>.rodata</td><td>ROM_INT</td><td>ROM_INT</td></tr>
+ *   <tr><td>.data</td><td>RAM_EXT</td><td>ROM_INT</td></tr>
+ *   <tr><td>.fast</td><td>RAM_INT</td><td>ROM_INT</td></tr>
+ *   <tr><td>.bss</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.work</td><td>RAM_EXT</td><td></td></tr>
+ *   <tr><td>.stack</td><td>RAM_INT</td><td></td></tr>
+ */
+
+
+MEMORY {
+	RAM_VEC (AIW) : ORIGIN = 0x40000000, LENGTH = 32k
+	RAM_INT (AIW) : ORIGIN = 0x40008000, LENGTH = 32k
+	RAM_USB (AIW) : ORIGIN = 0x7fd00000, LENGTH = 16k
+	RAM_EXT (AIW) : ORIGIN = 0xa0400000, LENGTH = 4M
+	ROM_INT (RX)  : ORIGIN = 0x00000000, LENGTH = 512k - 8k
+}
+
+REGION_ALIAS ("REGION_START", ROM_INT);
+REGION_ALIAS ("REGION_VECTOR", RAM_VEC);
+REGION_ALIAS ("REGION_TEXT", ROM_INT);
+REGION_ALIAS ("REGION_TEXT_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_RODATA", ROM_INT);
+REGION_ALIAS ("REGION_RODATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_DATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_USB);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_BSS", RAM_EXT);
+REGION_ALIAS ("REGION_WORK", RAM_EXT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT);
+
+INCLUDE linkcmds.armv4
diff --git a/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_plx800_ram b/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_plx800_ram
new file mode 100644
index 0000000000..2dcc6d233f
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_plx800_ram
@@ -0,0 +1,32 @@
+/**
+ * @file
+ *
+ * @brief Memory map for PLX800 (LPC2478).
+ */
+
+MEMORY {
+	RAM_INT : ORIGIN = 0x40000000, LENGTH = 64k
+	RAM_EXT : ORIGIN = 0xa0000000, LENGTH = 32M
+	ROM_INT : ORIGIN = 0x00000000, LENGTH = 512k - 8k
+	ROM_EXT : ORIGIN = 0x80000000, LENGTH = 4M
+}
+
+REGION_ALIAS ("REGION_START", RAM_EXT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", RAM_EXT);
+REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA", RAM_EXT);
+REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_INT);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_EXT);
+REGION_ALIAS ("REGION_BSS", RAM_EXT);
+REGION_ALIAS ("REGION_WORK", RAM_EXT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT);
+
+INCLUDE linkcmds.armv4
diff --git a/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_plx800_rom_int b/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_plx800_rom_int
new file mode 100644
index 0000000000..f00c1d8f93
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/linkcmds.lpc24xx_plx800_rom_int
@@ -0,0 +1,32 @@
+/**
+ * @file
+ *
+ * @brief Memory map for PLX800 (LPC2478).
+ */
+
+MEMORY {
+	RAM_INT : ORIGIN = 0x40000000, LENGTH = 64k
+	RAM_EXT : ORIGIN = 0xa0000000, LENGTH = 32M
+	ROM_INT : ORIGIN = 0x00000000, LENGTH = 512k - 8k
+	ROM_EXT : ORIGIN = 0x80000000, LENGTH = 4M
+}
+
+REGION_ALIAS ("REGION_START", ROM_INT);
+REGION_ALIAS ("REGION_VECTOR", RAM_INT);
+REGION_ALIAS ("REGION_TEXT", ROM_INT);
+REGION_ALIAS ("REGION_TEXT_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_RODATA", ROM_INT);
+REGION_ALIAS ("REGION_RODATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_DATA", RAM_EXT);
+REGION_ALIAS ("REGION_DATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_FAST_DATA", RAM_INT);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM_INT);
+REGION_ALIAS ("REGION_BSS", RAM_EXT);
+REGION_ALIAS ("REGION_WORK", RAM_EXT);
+REGION_ALIAS ("REGION_STACK", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE", RAM_INT);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT);
+
+INCLUDE linkcmds.armv4
diff --git a/bsps/arm/lpc24xx/start/linkcmds.lpc40xx_ea_ram b/bsps/arm/lpc24xx/start/linkcmds.lpc40xx_ea_ram
new file mode 100644
index 0000000000..d4535963cb
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/linkcmds.lpc40xx_ea_ram
@@ -0,0 +1 @@
+INCLUDE linkcmds.lpc17xx_ea_ram
diff --git a/bsps/arm/lpc24xx/start/linkcmds.lpc40xx_ea_rom_int b/bsps/arm/lpc24xx/start/linkcmds.lpc40xx_ea_rom_int
new file mode 100644
index 0000000000..612f4916d3
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/linkcmds.lpc40xx_ea_rom_int
@@ -0,0 +1 @@
+INCLUDE linkcmds.lpc17xx_ea_rom_int
diff --git a/bsps/arm/lpc24xx/start/start-config-emc-dynamic.c b/bsps/arm/lpc24xx/start/start-config-emc-dynamic.c
new file mode 100644
index 0000000000..3a08f0b49d
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/start-config-emc-dynamic.c
@@ -0,0 +1,271 @@
+/**
+ * @file
+ *
+ * @ingroup lpc24xx
+ *
+ * @brief BSP start EMC dynamic memory configuration.
+ */
+
+/*
+ * Copyright (c) 2011-2012 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp/start-config.h>
+#include <bsp/lpc24xx.h>
+
+/*
+ * FIXME: The NXP example code uses different values for the follwing two
+ * defines.  In the NXP example code they depend on the EMCCLK.  It is unclear
+ * how these values are determined.  The values from the NXP example code do
+ * not work.
+ */
+
+/* Use command delayed strategy */
+#define LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT 0x1
+
+#define LPC24XX_EMCDLYCTL_DEFAULT 0x1112
+
+BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config
+  lpc24xx_start_config_emc_dynamic [] = {
+#if defined(LPC24XX_EMC_MT48LC4M16A2)
+  /* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT */
+  {
+    /* 15.6 us */
+    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
+
+    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
+
+    /* Precharge command period 20 ns */
+    .trp = 1,
+
+    /* Active to precharge command period 44 ns */
+    .tras = 3,
+
+    /* FIXME */
+    .tsrex = 5,
+
+    /* FIXME */
+    .tapr = 2,
+
+    /* Data-in to active command period tWR + tRP */
+    .tdal = 4,
+
+    /* Write recovery time 15 ns */
+    .twr = 1,
+
+    /* Active to active command period 66 ns */
+    .trc = 4,
+
+    /* Auto refresh period 66 ns */
+    .trfc = 4,
+
+    /* Exit self refresh to active command period 75 ns */
+    .txsr = 5,
+
+    /* Active bank a to active bank b command period 15 ns */
+    .trrd = 1,
+
+    /* Load mode register to active or refresh command period 2 tCK */
+    .tmrd = 1
+  }
+#elif defined(LPC24XX_EMC_IS42S32800D7)
+  /* Dynamic Memory 0: ISSI IS42S32800D7 */
+  {
+    /* 15.6 us */
+    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
+
+    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
+
+    /* 20ns */
+    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
+
+    /* 45ns */
+    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
+
+    /* 70ns (tXSR) */
+    .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1),
+
+    /* 20ns (tRCD) */
+    .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
+
+    /* n clock cycles -> 38.8ns >= 35ns */
+    .tdal = LPC24XX_PS_TO_EMCCLK(35000, 0),
+
+    /* 14ns (tDPL) */
+    .twr = LPC24XX_PS_TO_EMCCLK(14000, 1),
+
+    /* 67.5ns */
+    .trc = LPC24XX_PS_TO_EMCCLK(67500, 1),
+
+    /* 67.5ns (tRC) */
+    .trfc = LPC24XX_PS_TO_EMCCLK(67500, 1),
+
+    /* 70ns */
+    .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1),
+
+    /* 14ns */
+    .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
+
+    /* 14ns */
+    .tmrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
+
+    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
+  }
+#elif defined(LPC24XX_EMC_W9825G2JB75I)
+  /* Dynamic Memory 0: Winbond W9825G2JB75I */
+  {
+    /* 15.6 us */
+    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
+
+    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
+
+    /* 20ns */
+    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
+
+    /* 45ns */
+    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
+
+    /* 75ns (tXSR) */
+    .tsrex = LPC24XX_PS_TO_EMCCLK(75000, 1),
+
+    /* 20ns (tRCD) */
+    .tapr = LPC24XX_PS_TO_EMCCLK(20000, 1),
+
+    /* tWR + tRP -> 2 * tCK + 20ns */
+    .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0),
+
+    /* (n + 1) clock cycles == 2 * tCK */
+    .twr = 1,
+
+    /* 65ns */
+    .trc = LPC24XX_PS_TO_EMCCLK(65000, 1),
+
+    /* 65ns (tRC) */
+    .trfc = LPC24XX_PS_TO_EMCCLK(65000, 1),
+
+    /* 75ns */
+    .txsr = LPC24XX_PS_TO_EMCCLK(50000, 1),
+
+    /* (n + 1) clock cycles == 2 * tCK */
+    .trrd = 1,
+
+    /* (n + 1) clock cycles == 2 * tCK (tRSC)*/
+    .tmrd = 1,
+
+    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
+  }
+#elif defined(LPC24XX_EMC_K4S561632E)
+  {
+    .refresh = 35,
+    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
+    .trp = 2,
+    .tras = 4,
+    .tsrex = 5,
+    .tapr = 1,
+    .tdal = 5,
+    .twr = 3,
+    .trc = 5,
+    .trfc = 5,
+    .txsr = 5,
+    .trrd = 3,
+    .tmrd = 2
+  }
+#elif defined(LPC24XX_EMC_IS42S32800B)
+  {
+    /* 15.6us */
+    .refresh = LPC24XX_PS_TO_EMCCLK(15600000, 0) / 16,
+
+    .readconfig = LPC24XX_EMC_DYNAMIC_READCONFIG_DEFAULT,
+
+    /* 20ns */
+    .trp = LPC24XX_PS_TO_EMCCLK(20000, 1),
+
+    /* 45ns */
+    .tras = LPC24XX_PS_TO_EMCCLK(45000, 1),
+
+    /* 70ns (tRC) */
+    .tsrex = LPC24XX_PS_TO_EMCCLK(70000, 1),
+
+    /* FIXME */
+    .tapr = LPC24XX_PS_TO_EMCCLK(40000, 1),
+
+    /* tWR + tRP -> 2 * tCK + 20ns */
+    .tdal = 2 + LPC24XX_PS_TO_EMCCLK(20000, 0),
+
+    /* (n + 1) clock cycles == 2 * tCK */
+    .twr = 1,
+
+    /* 70ns */
+    .trc = LPC24XX_PS_TO_EMCCLK(70000, 1),
+
+    /* 70ns */
+    .trfc = LPC24XX_PS_TO_EMCCLK(70000, 1),
+
+    /* 70ns (tRC) */
+    .txsr = LPC24XX_PS_TO_EMCCLK(70000, 1),
+
+    /* 14ns */
+    .trrd = LPC24XX_PS_TO_EMCCLK(14000, 1),
+
+    /* (n + 1) clock cycles == 2 * tCK */
+    .tmrd = 1,
+
+    .emcdlyctl = LPC24XX_EMCDLYCTL_DEFAULT
+  }
+#endif
+};
+
+BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_chip_config
+  lpc24xx_start_config_emc_dynamic_chip [] = {
+#if defined(LPC24XX_EMC_MT48LC4M16A2)
+  {
+    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
+
+    /*
+     * Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected
+     * writes.  4 banks, 12 row lines, 8 column lines.
+     */
+    .config = 0x280,
+
+    .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
+    .mode = 0xa0000000 | (0x23 << (1 + 2 + 8))
+  }
+#elif defined(LPC24XX_EMC_W9825G2JB75I) \
+  || defined(LPC24XX_EMC_IS42S32800D7) \
+  || defined(LPC24XX_EMC_IS42S32800B)
+  {
+    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
+
+    /* 32-bit data bus, 4 banks, 12 row lines, 9 column lines, RBC */
+    .config = 0x4480,
+
+    /* RAS based on tRCD = 20ns */
+    .rascas = EMC_DYN_RASCAS_RAS(2) | EMC_DYN_RASCAS_CAS(2, 0),
+
+    /* CAS 2, burst length 4 */
+    .mode = 0xa0000000 | (0x22 << (2 + 2 + 9))
+  }
+#elif defined(LPC24XX_EMC_K4S561632E)
+  {
+    .chip_select = (volatile lpc_emc_dynamic *) &EMC_DYN_CFG0,
+    .config = 0x680,
+    .rascas = EMC_DYN_RASCAS_RAS(3) | EMC_DYN_RASCAS_CAS(3, 0),
+    .mode = 0xa0000000 | (0x33 << 12)
+  }
+#endif
+};
+
+BSP_START_DATA_SECTION const size_t
+  lpc24xx_start_config_emc_dynamic_chip_count =
+    sizeof(lpc24xx_start_config_emc_dynamic_chip)
+      / sizeof(lpc24xx_start_config_emc_dynamic_chip [0]);
diff --git a/bsps/arm/lpc24xx/start/start-config-emc-static.c b/bsps/arm/lpc24xx/start/start-config-emc-static.c
new file mode 100644
index 0000000000..4a427664f6
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/start-config-emc-static.c
@@ -0,0 +1,133 @@
+/**
+ * @file
+ *
+ * @ingroup lpc24xx
+ *
+ * @brief BSP start EMC static memory configuration.
+ */
+
+/*
+ * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp/start-config.h>
+#include <bsp/lpc24xx.h>
+
+BSP_START_DATA_SECTION const lpc24xx_emc_static_chip_config
+   lpc24xx_start_config_emc_static_chip [] = {
+#if defined(LPC24XX_EMC_M29W160E)
+  /*
+   * Static Memory 1: Numonyx M29W160EB
+   *
+   * 1 clock cycle = 1/72MHz = 13.9ns
+   */
+  {
+    .chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_1,
+    .config = {
+      /*
+       * 16 bit, page mode disabled, active LOW chip select, extended wait
+       * disabled, writes not protected, byte lane state LOW/LOW (!).
+       */
+      .config = 0x81,
+
+      /* 1 clock cycles delay from the chip select 1 to the write enable */
+      .waitwen = 0,
+
+      /*
+       * 0 clock cycles delay from the chip select 1 or address change
+       * (whichever is later) to the output enable
+       */
+      .waitoen = 0,
+
+      /* 7 clock cycles delay from the chip select 1 to the read access */
+      .waitrd = 0x6,
+
+      /*
+       * 32 clock cycles delay for asynchronous page mode sequential accesses
+       */
+      .waitpage = 0x1f,
+
+      /* 5 clock cycles delay from the chip select 1 to the write access */
+      .waitwr = 0x3,
+
+      /* 16 bus turnaround cycles */
+      .waitrun = 0xf
+    }
+  }
+#elif defined(LPC24XX_EMC_M29W320E70)
+  /* Static Memory 0: M29W320E70 */
+  {
+    .chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_0,
+    .config = {
+      /*
+       * 16 bit, page mode disabled, active LOW chip select, extended wait
+       * disabled, writes not protected, byte lane state LOW/LOW.
+       */
+      .config = 0x81,
+
+      /* 30ns (tWHWL) */
+      .waitwen = LPC24XX_PS_TO_EMCCLK(30000, 1),
+
+      /* 0ns */
+      .waitoen = LPC24XX_PS_TO_EMCCLK(0, 1),
+
+      /* 70ns (tAVQV, tELQV) */
+      .waitrd = LPC24XX_PS_TO_EMCCLK(70000, 1),
+
+      /* 70ns (tAVQV, tELQV) */
+      .waitpage = LPC24XX_PS_TO_EMCCLK(70000, 1),
+
+      /* max(30ns (tWHWL) + 45ns (tWLWH), 70ns (tAVAV)) */
+      .waitwr = LPC24XX_PS_TO_EMCCLK(75000, 2),
+
+      /* 25ns (tEHQZ) */
+      .waitrun = LPC24XX_PS_TO_EMCCLK(25000, 1)
+    }
+  }
+#elif defined(LPC24XX_EMC_SST39VF3201)
+  /* Static Memory 0: SST39VF3201 */
+  {
+    .chip_select = (volatile lpc_emc_static *) EMC_STA_BASE_0,
+    .config = {
+      /*
+       * 16 bit, page mode disabled, active LOW chip select, extended wait
+       * disabled, writes not protected, byte lane state LOW/LOW.
+       */
+      .config = 0x81,
+
+      /* 0ns (tCS, tAS) */
+      .waitwen = LPC24XX_PS_TO_EMCCLK(0, 1),
+
+      /* 0ns (tOES) */
+      .waitoen = LPC24XX_PS_TO_EMCCLK(0, 1),
+
+      /* 70ns (tRC) */
+      .waitrd = LPC24XX_PS_TO_EMCCLK(70000, 1),
+
+      /* 70ns (tRC) */
+      .waitpage = LPC24XX_PS_TO_EMCCLK(70000, 1),
+
+      /* 20ns (tCHZ, TOHZ) */
+      .waitwr = LPC24XX_PS_TO_EMCCLK(20000, 2),
+
+      /* 20ns (tCHZ, TOHZ) */
+      .waitrun = LPC24XX_PS_TO_EMCCLK(20000, 1)
+    }
+  }
+#endif
+};
+
+BSP_START_DATA_SECTION const size_t
+  lpc24xx_start_config_emc_static_chip_count =
+    sizeof(lpc24xx_start_config_emc_static_chip)
+      / sizeof(lpc24xx_start_config_emc_static_chip [0]);
diff --git a/bsps/arm/lpc24xx/start/start-config-mpu.c b/bsps/arm/lpc24xx/start/start-config-mpu.c
new file mode 100644
index 0000000000..9d9846c69a
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/start-config-mpu.c
@@ -0,0 +1,86 @@
+/**
+ * @file
+ *
+ * @ingroup lpc24xx
+ *
+ * @brief BSP start MPU configuration.
+ */
+
+/*
+ * Copyright (c) 2011-2012 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp/start-config.h>
+
+#ifdef ARM_MULTILIB_ARCH_V7M
+  BSP_START_DATA_SECTION const ARMV7M_MPU_Region
+    lpc24xx_start_config_mpu_region [] = {
+      #if defined(LPC24XX_EMC_IS42S32800D7) \
+        || defined(LPC24XX_EMC_W9825G2JB75I) \
+        || defined(LPC24XX_EMC_IS42S32800B)
+        ARMV7M_MPU_REGION_INITIALIZER(
+          0,
+          0x00000000,
+          ARMV7M_MPU_SIZE_512_KB,
+          ARMV7M_MPU_ATTR_RX
+        ),
+        ARMV7M_MPU_REGION_INITIALIZER(
+          1,
+          0x10000000,
+          ARMV7M_MPU_SIZE_64_KB,
+          ARMV7M_MPU_ATTR_RWX
+        ),
+        ARMV7M_MPU_REGION_INITIALIZER(
+          2,
+          0x20000000,
+          ARMV7M_MPU_SIZE_32_KB,
+          ARMV7M_MPU_ATTR_RWX
+        ),
+        ARMV7M_MPU_REGION_INITIALIZER(
+          3,
+          0xa0000000,
+          ARMV7M_MPU_SIZE_32_MB,
+          ARMV7M_MPU_ATTR_RWX
+        ),
+        ARMV7M_MPU_REGION_INITIALIZER(
+          4,
+          0x20080000,
+          ARMV7M_MPU_SIZE_128_KB,
+          ARMV7M_MPU_ATTR_IO
+        ),
+        ARMV7M_MPU_REGION_INITIALIZER(
+          5,
+          0x40000000,
+          ARMV7M_MPU_SIZE_1_MB,
+          ARMV7M_MPU_ATTR_IO
+        ),
+        #if defined(LPC24XX_EMC_M29W320E70) \
+          || defined(LPC24XX_EMC_SST39VF3201)
+          ARMV7M_MPU_REGION_INITIALIZER(
+            6,
+            0x80000000,
+            ARMV7M_MPU_SIZE_4_MB,
+            ARMV7M_MPU_ATTR_RWX
+          ),
+        #else
+          ARMV7M_MPU_REGION_DISABLED_INITIALIZER(6),
+        #endif
+        ARMV7M_MPU_REGION_DISABLED_INITIALIZER(7)
+     #endif
+  };
+
+  BSP_START_DATA_SECTION const size_t
+    lpc24xx_start_config_mpu_region_count =
+      sizeof(lpc24xx_start_config_mpu_region)
+        / sizeof(lpc24xx_start_config_mpu_region [0]);
+#endif
diff --git a/bsps/arm/lpc24xx/start/start-config-pinsel.c b/bsps/arm/lpc24xx/start/start-config-pinsel.c
new file mode 100644
index 0000000000..db44099664
--- /dev/null
+++ b/bsps/arm/lpc24xx/start/start-config-pinsel.c
@@ -0,0 +1,74 @@
+/**
+ * @file
+ *
+ * @ingroup lpc24xx
+ *
+ * @brief BSP start pin selection configuration.
+ */
+
+/*
+ * Copyright (c) 2011-2012 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp/start-config.h>
+
+BSP_START_DATA_SECTION const lpc24xx_pin_range
+  lpc24xx_start_config_pinsel [] = {
+#if defined(LPC24XX_EMC_MT48LC4M16A2) \
+  && defined(LPC24XX_EMC_M29W160E)
+  LPC24XX_PIN_EMC_A_0_20,
+  LPC24XX_PIN_EMC_D_0_15,
+  LPC24XX_PIN_EMC_RAS,
+  LPC24XX_PIN_EMC_CAS,
+  LPC24XX_PIN_EMC_WE,
+  LPC24XX_PIN_EMC_DYCS_0,
+  LPC24XX_PIN_EMC_CLK_0,
+  LPC24XX_PIN_EMC_CKE_0,
+  LPC24XX_PIN_EMC_DQM_0,
+  LPC24XX_PIN_EMC_DQM_1,
+  LPC24XX_PIN_EMC_OE,
+  LPC24XX_PIN_EMC_CS_1,
+#endif
+#if (defined(LPC24XX_EMC_IS42S32800D7) || defined(LPC24XX_EMC_W9825G2JB75I)) \
+  && (defined(LPC24XX_EMC_M29W320E70) || defined(LPC24XX_EMC_SST39VF3201))
+  LPC24XX_PIN_EMC_A_0_22,
+  LPC24XX_PIN_EMC_D_0_31,
+  LPC24XX_PIN_EMC_RAS,
+  LPC24XX_PIN_EMC_CAS,
+  LPC24XX_PIN_EMC_WE,
+  LPC24XX_PIN_EMC_DYCS_0,
+  LPC24XX_PIN_EMC_CLK_0,
+  LPC24XX_PIN_EMC_CKE_0,
+  LPC24XX_PIN_EMC_DQM_0,
+  LPC24XX_PIN_EMC_DQM_1,
+  LPC24XX_PIN_EMC_DQM_2,
+  LPC24XX_PIN_EMC_DQM_3,
+  LPC24XX_PIN_EMC_OE,
+  LPC24XX_PIN_EMC_CS_0,
+#endif
+#if defined(LPC24XX_EMC_IS42S32800B)
+  LPC24XX_PIN_EMC_A_0_14,
+  LPC24XX_PIN_EMC_D_0_31,
+  LPC24XX_PIN_EMC_RAS,
+  LPC24XX_PIN_EMC_CAS,
+  LPC24XX_PIN_EMC_WE,
+  LPC24XX_PIN_EMC_DYCS_0,
+  LPC24XX_PIN_EMC_CLK_0,
+  LPC24XX_PIN_EMC_CKE_0,
+  LPC24XX_PIN_EMC_DQM_0,
+  LPC24XX_PIN_EMC_DQM_1,
+  LPC24XX_PIN_EMC_DQM_2,
+  LPC24XX_PIN_EMC_DQM_3,
+#endif
+  LPC24XX_PIN_TERMINAL
+};