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authorChristian Mauderer <christian.mauderer@embedded-brains.de>2023-05-09 10:46:50 +0200
committerChristian Mauderer <christian.mauderer@embedded-brains.de>2023-05-22 09:43:48 +0200
commit38ad41ecceb7c9f7549e58ddf485fc893f8b3c35 (patch)
tree3e9112d3b29f3bf705dfa290c15c599e0cb7924b /bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_flexram_allocate.c
parentUpdate company name (diff)
downloadrtems-38ad41ecceb7c9f7549e58ddf485fc893f8b3c35.tar.bz2
bsp/imxrt: Update support library from mcux-sdk
This imports new files from the mcux-sdk support library. NXP now offers the library as a git repository instead of a zip package. The git repository supports multiple CPUs from the i.MXRT family: https://github.com/nxp-mcuxpresso/mcux-sdk.git The imported files are from revision 2b9354539e6e4f722749e87b0bdc22966dc080d9 This revision is the same as MCUXpresso 2.13.0 with small bug fixes. For importing the files, a script has been used, that parses the mcux-sdk cmake files and creates the yaml files for RTEMS: https://raw.githubusercontent.com/c-mauderer/nxp-mcux-sdk/d21c3e61eb8602b2cf8f45fed0afa50c6aee932f/export_to_RTEMS.py
Diffstat (limited to '')
-rw-r--r--bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_flexram_allocate.c92
1 files changed, 92 insertions, 0 deletions
diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_flexram_allocate.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_flexram_allocate.c
new file mode 100644
index 0000000000..32d99f7b4c
--- /dev/null
+++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_flexram_allocate.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2019-2021 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexram_allocate.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.soc_flexram_allocate"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM
+ * This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate
+ * is needed.
+ * param config allocate configuration.
+ * retval kStatus_InvalidArgument the argument is invalid
+ * kStatus_Success allocate success
+ */
+status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config)
+{
+ assert(config != NULL);
+
+ uint8_t dtcmBankNum = config->dtcmBankNum;
+ uint8_t itcmBankNum = config->itcmBankNum;
+ uint8_t ocramBankNum = config->ocramBankNum;
+ uint8_t i = 0U;
+ uint32_t bankCfg = 0U;
+ status_t status = kStatus_Success;
+ uint32_t tempGPR17 = 0U;
+ uint32_t tempGPR18 = 0U;
+
+ /* check the arguments */
+ if ((uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum))
+ {
+ status = kStatus_InvalidArgument;
+ }
+ else
+ {
+ /* flexram bank config value */
+ for (i = 0U; i < (uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS; i++)
+ {
+ if (i < ocramBankNum)
+ {
+ bankCfg |= ((uint32_t)kFLEXRAM_BankOCRAM) << (i * 2U);
+ continue;
+ }
+
+ if (i < (dtcmBankNum + ocramBankNum))
+ {
+ bankCfg |= ((uint32_t)kFLEXRAM_BankDTCM) << (i * 2U);
+ continue;
+ }
+
+ if (i < (dtcmBankNum + ocramBankNum + itcmBankNum))
+ {
+ bankCfg |= ((uint32_t)kFLEXRAM_BankITCM) << (i * 2U);
+ continue;
+ }
+ }
+
+ tempGPR17 = IOMUXC_GPR->GPR17;
+ tempGPR18 = IOMUXC_GPR->GPR18;
+
+ IOMUXC_GPR->GPR17 = (tempGPR17 & ~IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK) | (bankCfg & 0xFFFFU);
+ IOMUXC_GPR->GPR18 = (tempGPR18 & ~IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK) | ((bankCfg >> 16) & 0xFFFFU);
+
+ /* select ram allocate source from FLEXRAM_BANK_CFG */
+ FLEXRAM_SetAllocateRamSrc(kFLEXRAM_BankAllocateThroughBankCfg);
+ }
+
+ return status;
+}