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authorSebastian Huber <sebastian.huber@embedded-brains.de>2024-03-11 14:18:46 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2024-03-11 14:22:53 +0100
commit283f783d5d884c0f0f823c5f2d24ebaa97624d88 (patch)
treece2c484326bbae08ee5be736fadb98e7b7990b62 /bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
parentbsps/powerpc: Fix include order (diff)
downloadrtems-283f783d5d884c0f0f823c5f2d24ebaa97624d88.tar.bz2
aarch64/zynqmp: Fix UART base addresses and IRQ
The base addresses and IRQ numbers for UART 0 and 1 were interchanged. Fix this and set BSP_CONSOLE_MINOR to 0 for this BSP family.
Diffstat (limited to '')
-rw-r--r--bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h b/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
index 2cbe99f863..024fd0d89a 100644
--- a/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
+++ b/bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h
@@ -56,8 +56,8 @@ extern "C" {
#define ZYNQMP_IRQ_QSPI 47
#define ZYNQMP_IRQ_I2C_0 49
#define ZYNQMP_IRQ_I2C_1 50
-#define ZYNQMP_IRQ_UART_0 54
-#define ZYNQMP_IRQ_UART_1 53
+#define ZYNQMP_IRQ_UART_0 53
+#define ZYNQMP_IRQ_UART_1 54
#define ZYNQMP_IRQ_ETHERNET_0 89
#define ZYNQMP_IRQ_ETHERNET_1 91
#define ZYNQMP_IRQ_ETHERNET_2 93