diff options
| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2021-07-26 15:43:00 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2021-09-21 08:58:32 -0500 |
| commit | 5f652cb27e0134362e0160135124352539315845 (patch) | |
| tree | a370df31b31472331566975319b8fc9fa950d4d4 /bsps/aarch64/shared/start/start.S | |
| parent | bsps/gicv2: Allow BSPs to define IRQ attributes (diff) | |
| download | rtems-5f652cb27e0134362e0160135124352539315845.tar.bz2 | |
cpukit: Add AArch64 SMP Support
This adds SMP support for AArch64 in cpukit and for the ZynqMP BSPs.
Diffstat (limited to '')
| -rw-r--r-- | bsps/aarch64/shared/start/start.S | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/bsps/aarch64/shared/start/start.S b/bsps/aarch64/shared/start/start.S index f4c39dacdf..bc6a855217 100644 --- a/bsps/aarch64/shared/start/start.S +++ b/bsps/aarch64/shared/start/start.S @@ -166,21 +166,21 @@ _el1_start: #ifdef RTEMS_SMP /* Read MPIDR and get current processor index */ mrs x7, mpidr_el1 - and x7, #0xff + and x7, x7, #0xff #endif #ifdef RTEMS_SMP /* * Get current per-CPU control and store it in PL1 only Thread ID - * Register (TPIDRPRW). + * Register (TPIDR_EL1). */ #ifdef AARCH64_MULTILIB_ARCH_V8_ILP32 ldr w1, =_Per_CPU_Information #else ldr x1, =_Per_CPU_Information #endif - add x1, x1, x7, asl #PER_CPU_CONTROL_SIZE_LOG2 - mcr p15, 0, x1, c13, c0, 4 + add x1, x1, x7, lsl #PER_CPU_CONTROL_SIZE_LOG2 + msr TPIDR_EL1, x1 #endif @@ -201,8 +201,8 @@ _el1_start: #endif add x3, x1, x2 - /* Save original DAIF value */ - mrs x4, DAIF + /* Disable interrupts */ + msr DAIFSet, #0x2 #ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION mov x8, XZR |