2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>

	* e500/mmu/mmu.c, mpc505/ictrl/ictrl.c, mpc505/timer/timer.c,
	mpc5xx/ictrl/ictrl.c, mpc5xx/timer/timer.c,
	mpc6xx/altivec/vec_sup.c, mpc6xx/clock/c_clock.c,
	mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/pte121.c,
	mpc8260/timer/timer.c, mpc8xx/timer/timer.c, new-exceptions/cpu.c,
	new-exceptions/bspsupport/ppc_exc_initialize.c,
	ppc403/clock/clock.c, ppc403/console/console.c,
	ppc403/console/console.c.polled, ppc403/console/console405.c,
	ppc403/irq/ictrl.c, ppc403/tty_drv/tty_drv.c,
	rtems/powerpc/cache.h, shared/include/powerpc-utility.h, shared/src/cache.c:
	Use "__asm__" instead of "asm" for improved c99-compliance.

24 files changed, 114 insertions, 100 deletions

diff --git a/c/src/lib/libcpu/powerpc/ChangeLog b/c/src/lib/libcpu/powerpc/ChangeLog
index f4183a1a24..b6679a969a 100644
--- a/c/src/lib/libcpu/powerpc/ChangeLog
+++ b/c/src/lib/libcpu/powerpc/ChangeLog
@@ -1,3 +1,17 @@
+2011-02-11	Ralf Corsépius <ralf.corsepius@rtems.org>
+
+	* e500/mmu/mmu.c, mpc505/ictrl/ictrl.c, mpc505/timer/timer.c,
+	mpc5xx/ictrl/ictrl.c, mpc5xx/timer/timer.c,
+	mpc6xx/altivec/vec_sup.c, mpc6xx/clock/c_clock.c,
+	mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/pte121.c,
+	mpc8260/timer/timer.c, mpc8xx/timer/timer.c, new-exceptions/cpu.c,
+	new-exceptions/bspsupport/ppc_exc_initialize.c,
+	ppc403/clock/clock.c, ppc403/console/console.c,
+	ppc403/console/console.c.polled, ppc403/console/console405.c,
+	ppc403/irq/ictrl.c, ppc403/tty_drv/tty_drv.c,
+	rtems/powerpc/cache.h, shared/include/powerpc-utility.h, shared/src/cache.c:
+	Use "__asm__" instead of "asm" for improved c99-compliance.
+
 2011-02-02	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* configure.ac: Require autoconf-2.68, automake-1.11.1.
diff --git a/c/src/lib/libcpu/powerpc/e500/mmu/mmu.c b/c/src/lib/libcpu/powerpc/e500/mmu/mmu.c
index 0c39800206..7fbfa6e5f5 100644
--- a/c/src/lib/libcpu/powerpc/e500/mmu/mmu.c
+++ b/c/src/lib/libcpu/powerpc/e500/mmu/mmu.c
@@ -99,9 +99,9 @@
 /* Factory to generate inline macros for accessing the MAS registers */
 #define __RDWRMAS(mas,rmas)	\
 	static inline uint32_t _read_MAS##mas(void)	                                 \
-	{ uint32_t x; asm volatile("mfspr %0, %1": "=r"(x):"i"(rmas)); return x; } \
+	{ uint32_t x; __asm__ volatile("mfspr %0, %1": "=r"(x):"i"(rmas)); return x; } \
 	static inline void _write_MAS##mas(uint32_t x)                             \
-	{             asm volatile("mtspr %1, %0":: "r"(x),"i"(rmas)); }
+	{             __asm__ volatile("mtspr %1, %0":: "r"(x),"i"(rmas)); }
 
 __RDWRMAS(0,FSL_EIS_MAS0)
 __RDWRMAS(1,FSL_EIS_MAS1)
diff --git a/c/src/lib/libcpu/powerpc/mpc505/ictrl/ictrl.c b/c/src/lib/libcpu/powerpc/mpc505/ictrl/ictrl.c
index bb297e7d84..51db6a62c1 100644
--- a/c/src/lib/libcpu/powerpc/mpc505/ictrl/ictrl.c
+++ b/c/src/lib/libcpu/powerpc/mpc505/ictrl/ictrl.c
@@ -36,7 +36,7 @@ static ExtIsrHandler extIrqHandlers[NUM_IRQS] =
 static rtems_isr extIsr_( rtems_vector_number i )
 {
 #define BIT_NUMBER(val, bit) \
-    asm volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
+    __asm__ volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
 
   int bit;
   (void)i;
diff --git a/c/src/lib/libcpu/powerpc/mpc505/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc505/timer/timer.c
index edbaded21d..b8f0c7e28b 100644
--- a/c/src/lib/libcpu/powerpc/mpc505/timer/timer.c
+++ b/c/src/lib/libcpu/powerpc/mpc505/timer/timer.c
@@ -22,7 +22,7 @@ static unsigned int volatile lastInitValue;
 
 void benchmark_timer_initialize( void )
 {
-  asm volatile( " mftb %0": "=r" (lastInitValue) );
+  __asm__ volatile( " mftb %0": "=r" (lastInitValue) );
 }
 
 /*
@@ -43,7 +43,7 @@ void benchmark_timer_initialize( void )
 int benchmark_timer_read( void )
 {
   uint32_t   value;
-  asm volatile ( " mftb %0": "=r" (value) );
+  __asm__ volatile ( " mftb %0": "=r" (value) );
   return value - lastInitValue;
 }
 
diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/ictrl/ictrl.c b/c/src/lib/libcpu/powerpc/mpc5xx/ictrl/ictrl.c
index bb297e7d84..51db6a62c1 100644
--- a/c/src/lib/libcpu/powerpc/mpc5xx/ictrl/ictrl.c
+++ b/c/src/lib/libcpu/powerpc/mpc5xx/ictrl/ictrl.c
@@ -36,7 +36,7 @@ static ExtIsrHandler extIrqHandlers[NUM_IRQS] =
 static rtems_isr extIsr_( rtems_vector_number i )
 {
 #define BIT_NUMBER(val, bit) \
-    asm volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
+    __asm__ volatile ( "cntlzw %0, %1; srawi %0, %0, 1": "=r" (bit) : "r" (val) );
 
   int bit;
   (void)i;
diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c
index 17d8f8b5e5..f16c5b3c39 100644
--- a/c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c
+++ b/c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c
@@ -64,7 +64,7 @@ static inline uint32_t get_itimer(void)
 {
    uint32_t ret;
 
-   asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
+   __asm__ volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
 
    return ret;
 }
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c b/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c
index ae9a5097a2..4fa16e5aa8 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c
@@ -141,8 +141,8 @@ rst_MSR_VE(uint32_t old)
  */
 
 static void dummy(void) __attribute__((noinline));
-/* add (empty) asm statement to make sure this isn't optimized away */
-static void dummy(void) { asm volatile(""); }
+/* add (empty) __asm__ statement to make sure this isn't optimized away */
+static void dummy(void) { __asm__ volatile(""); }
 
 static unsigned probe_r1(void) __attribute__((noinline));
 static unsigned probe_r1(void)
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c b/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c
index 0f7fe86ef0..9983a78fdb 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c
@@ -133,7 +133,7 @@ int decr;
   do {
   register uint32_t flags;
   rtems_interrupt_disable(flags);
-  asm volatile (
+  __asm__ volatile (
     "mfdec %0; add %0, %0, %1; mtdec %0"
     : "=&r"(decr)
     : "r"(Clock_Decrementer_value));
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c
index c52e1b6249..65dc92a754 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c
@@ -124,7 +124,7 @@ SPR_RO (HID0);
 static void
 set_hid0_sync (unsigned long val)
 {
-  asm volatile (
+  __asm__ volatile (
     "	sync			\n"
     "	isync			\n"
     "	mtspr	%0, %1	\n"
@@ -221,7 +221,7 @@ do_dssall (void)
      * rely on consistent compiler flags).
      */
 #define DSSALL	0x7e00066c      /* dssall opcode */
-    asm volatile ("	.long %0"::"i" (DSSALL));
+    __asm__ volatile ("	.long %0"::"i" (DSSALL));
 #undef  DSSALL
   }
 }
@@ -287,7 +287,7 @@ check_bat_size (unsigned long size)
   if (0xffffffff == size) {
     bit = 32;
   } else {
-    asm volatile ("	cntlzw %0, %1":"=r" (bit):"r" (size));
+    __asm__ volatile ("	cntlzw %0, %1":"=r" (bit):"r" (size));
     bit = 31 - bit;
     if (1 << bit != size)
       return -1;
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h
index c7f68a97e8..28e1748a13 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h
@@ -65,7 +65,7 @@ extern int getdbat(int bat_index, unsigned long *pu, unsigned long *pl);
 /* Same as getdbat but reads IBAT */
 extern int getibat(int bat_index, unsigned long *pu, unsigned long *pl);
 
-/* Do not use the asm routines; they are obsolete; use setdbat() instead */
+/* Do not use the __asm__ routines; they are obsolete; use setdbat() instead */
 extern void asm_setdbat0(unsigned int uperPart, unsigned int lowerPart);
 extern void asm_setdbat1(unsigned int uperPart, unsigned int lowerPart);
 extern void asm_setdbat2(unsigned int uperPart, unsigned int lowerPart);
diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c
index 4389d392e4..f11727f62e 100644
--- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c
@@ -157,7 +157,7 @@
 static uint32_t
 seg2vsid (uint32_t ea)
 {
-  asm volatile ("mfsrin %0, %0":"=r" (ea):"0" (ea));
+  __asm__ volatile ("mfsrin %0, %0":"=r" (ea):"0" (ea));
   return ea & ((1 << LD_VSID_SIZE) - 1);
 }
 #else
@@ -539,9 +539,9 @@ triv121PgTblMap (Triv121PgTbl pt,
               uint32_t flags;
               rtems_interrupt_disable (flags);
               /* order setting 'v' after writing everything else */
-              asm volatile ("eieio":::"memory");
+              __asm__ volatile ("eieio":::"memory");
               pte->v = 1;
-              asm volatile ("sync":::"memory");
+              __asm__ volatile ("sync":::"memory");
               rtems_interrupt_enable (flags);
             } else {
               pte->v = 1;
@@ -869,7 +869,7 @@ triv121UnmapEa (unsigned long ea)
   rtems_interrupt_disable (flags);
   pte->v = 0;
   do_dssall ();
-  asm volatile ("	sync		\n\t"
+  __asm__ volatile ("	sync		\n\t"
                 "	tlbie %0	\n\t"
                 "	eieio		\n\t"
                 "	tlbsync		\n\t"
@@ -916,7 +916,7 @@ do_dssall (void)
      * rely on consistent compiler flags).
      */
 #define DSSALL	0x7e00066c      /* dssall opcode */
-    asm volatile ("	.long %0"::"i" (DSSALL));
+    __asm__ volatile ("	.long %0"::"i" (DSSALL));
 #undef  DSSALL
   }
 }
@@ -946,21 +946,21 @@ triv121ChangeEaAttributes (unsigned long ea, int wimg, int pp)
   if (wimg < 0 && pp < 0)
     return pte;
 
-  asm volatile ("mfmsr %0":"=r" (msr));
+  __asm__ volatile ("mfmsr %0":"=r" (msr));
 
   /* switch MMU and IRQs off */
   SYNC_LONGJMP (msr & ~(MSR_EE | MSR_DR | MSR_IR));
 
   pte->v = 0;
   do_dssall ();
-  asm volatile ("sync":::"memory");
+  __asm__ volatile ("sync":::"memory");
   if (wimg >= 0)
     pte->wimg = wimg;
   if (pp >= 0)
     pte->pp = pp;
-  asm volatile ("tlbie %0; eieio"::"r" (ea):"memory");
+  __asm__ volatile ("tlbie %0; eieio"::"r" (ea):"memory");
   pte->v = 1;
-  asm volatile ("tlbsync; sync":::"memory");
+  __asm__ volatile ("tlbsync; sync":::"memory");
 
   /* restore, i.e., switch MMU and IRQs back on */
   SYNC_LONGJMP (msr);
diff --git a/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c
index be77f4fd14..65655aa6fb 100644
--- a/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c
+++ b/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c
@@ -60,7 +60,7 @@ static inline uint32_t   get_itimer(void)
 {
    uint32_t   ret;
 
-   asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
+   __asm__ volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
 
    return ret;
 }
diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c
index 3258d46b49..b0bacfafb7 100644
--- a/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c
+++ b/c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c
@@ -57,7 +57,7 @@ static inline uint32_t   get_itimer(void)
 {
    uint32_t   ret;
 
-   asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
+   __asm__ volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
 
    return ret;
 }
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
index d8b14320a1..7ff0e5c575 100644
--- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
+++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
@@ -30,8 +30,8 @@
 
 uint32_t ppc_exc_cache_wb_check = 1;
 
-#define MTIVPR(prefix) asm volatile ("mtivpr %0" : : "r" (prefix))
-#define MTIVOR(x, vec) asm volatile ("mtivor"#x" %0" : : "r" (vec))
+#define MTIVPR(prefix) __asm__ volatile ("mtivpr %0" : : "r" (prefix))
+#define MTIVOR(x, vec) __asm__ volatile ("mtivor"#x" %0" : : "r" (vec))
 
 static void ppc_exc_initialize_booke(void)
 {
@@ -94,7 +94,7 @@ rtems_status_code ppc_exc_initialize(
   /* Assembly code needs SDA_BASE in r13 (SVR4 or EABI). Make sure
    * early init code put it there.
    */
-  asm volatile (
+  __asm__ volatile (
     "lis %0, _SDA_BASE_@h\n"
     "ori %0, %0, _SDA_BASE_@l\n"
     "mr  %1, 13\n"
@@ -174,7 +174,7 @@ rtems_status_code ppc_exc_initialize(
      * ATM.
      */
     p = (p + 31U) & ~31U;
-    asm volatile ("dcbz 0, %0"::"b" (p));
+    __asm__ volatile ("dcbz 0, %0"::"b" (p));
     /* If we make it thru here then things seem to be OK */
   }
 
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c b/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c
index 0c269f71e6..c1106ed910 100644
--- a/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c
+++ b/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c
@@ -132,7 +132,7 @@ void _CPU_Context_Initialize(
    */
   { uint32_t    r2 = 0;
     unsigned    r13 = 0;
-    asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
+    __asm__ volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
 
     the_context->gpr2 = r2;
     the_context->gpr13 = r13;
@@ -140,7 +140,7 @@ void _CPU_Context_Initialize(
 #elif (PPC_ABI == PPC_ABI_EABI)
   { uint32_t    r2 = 0;
     unsigned    r13 = 0;
-    asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
+    __asm__ volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
 
     the_context->gpr2 = r2;
     the_context->gpr13 = r13;
diff --git a/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c b/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c
index 513049e1f8..e121dfbb3a 100644
--- a/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c
+++ b/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c
@@ -73,9 +73,9 @@ static inline uint32_t   get_itimer(void)
     register uint32_t   rc;
 
 #ifndef ppc405 /* this is a ppc403 */
-    asm volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */
+    __asm__ volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */
 #else /* ppc405 */
-    asm volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405GP TBL */
+    __asm__ volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405GP TBL */
 #endif /* ppc405 */
 
     return rc;
@@ -135,11 +135,11 @@ void Clock_isr(void* handle)
         /* XXX: count these! this should never happen :-) */
       }
 
-      asm volatile ("mtspr 0x3db, %0" :: "r"
+      __asm__ volatile ("mtspr 0x3db, %0" :: "r"
                          (clicks_til_next_interrupt)); /* PIT */
   }
 
-    asm volatile ( "mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */
+    __asm__ volatile ( "mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */
 
     Clock_driver_ticks++;
 
@@ -160,7 +160,7 @@ int ClockIsOn(const rtems_irq_connect_data* unused)
 {
     register uint32_t   tcr;
 
-    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
+    __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
 
     return (tcr & 0x04000000) != 0;
 }
@@ -171,11 +171,11 @@ void ClockOff(
 {
     register uint32_t   tcr;
 
-    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
+    __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
 
     tcr &= ~ 0x04400000;
 
-    asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
+    __asm__ volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
 }
 
 void ClockOn(
@@ -191,16 +191,16 @@ void ClockOn(
     Clock_driver_ticks = 0;
 
 #ifndef ppc405 /* this is a ppc403 */
-    asm volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */
+    __asm__ volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */
     if (bsp_timer_internal_clock) {
 	iocr &= ~4; /* timer clocked from system clock */
     }
     else {
 	iocr |= 4; /* select external timer clock */
     }
-    asm volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */
+    __asm__ volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */
 
-    asm volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */
+    __asm__ volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */
     if (((pvr & 0xffff0000) >> 16) != 0x0020)
       return; /* Not a ppc403 */
 
@@ -215,14 +215,14 @@ void ClockOn(
       auto_restart = true;
 
 #else /* ppc405 */
-    asm volatile ("mfdcr %0, 0x0b2" : "=r" (iocr));  /*405GP CPC0_CR1 */
+    __asm__ volatile ("mfdcr %0, 0x0b2" : "=r" (iocr));  /*405GP CPC0_CR1 */
     if (bsp_timer_internal_clock) {
 	iocr &=~0x800000	;/* timer clocked from system clock CETE*/
     }
     else {
 	iocr |= 0x800000; /* select external timer clock CETE*/
     }
-    asm volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */
+    __asm__ volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */
 
      /*
       * Enable auto restart
@@ -238,7 +238,7 @@ void ClockOn(
       * Set PIT value
       */
 
-    asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
+    __asm__ volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
 
      /*
       * Set timer to autoreload, bit TCR->ARE = 1  0x0400000
@@ -246,10 +246,10 @@ void ClockOn(
       */
     tick_time = get_itimer() + pit_value;
 
-    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
+    __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
     tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000);
 #if 1
-    asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
+    __asm__ volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
 #endif
 
 }
diff --git a/c/src/lib/libcpu/powerpc/ppc403/console/console.c b/c/src/lib/libcpu/powerpc/ppc403/console/console.c
index a7bb3dec51..fdba1ec751 100644
--- a/c/src/lib/libcpu/powerpc/ppc403/console/console.c
+++ b/c/src/lib/libcpu/powerpc/ppc403/console/console.c
@@ -351,12 +351,12 @@ spiInitialize(void)
    * select RTS/CTS hardware handshake lines,
    * select clock source
    */
-  asm volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
+  __asm__ volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
 
   tmp &= ~3;
   tmp |= (bsp_serial_external_clock ? 2 : 0) | 1;
 
-  asm volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
+  __asm__ volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
 
   /* clear any receive (error) status */
   port->SPLS = (LSRDataReady   | LSRFramingError | LSROverrunError |
diff --git a/c/src/lib/libcpu/powerpc/ppc403/console/console.c.polled b/c/src/lib/libcpu/powerpc/ppc403/console/console.c.polled
index eaf0975091..363db68c19 100644
--- a/c/src/lib/libcpu/powerpc/ppc403/console/console.c.polled
+++ b/c/src/lib/libcpu/powerpc/ppc403/console/console.c.polled
@@ -146,11 +146,11 @@ rtems_device_driver console_initialize(
   extern uint32_t bsp_serial_rate;
 
   /* Initialise the serial port */
-  asm volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
+  __asm__ volatile ("mfdcr %0, 0xa0" : "=r" (tmp)); /* IOCR */
   tmp &= ~3;
   tmp |= (bsp_serial_external_clock ? 2 : 0) |
       (bsp_serial_cts_rts ? 1 : 0);
-  asm volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
+  __asm__ volatile ("mtdcr 0xa0, %0" : "=r" (tmp) : "0" (tmp)); /* IOCR */
   port->SPLS = (LSRDataReady | LSRFramingError | LSROverrunError |
          LSRParityError | LSRBreakInterrupt);
   tmp = bsp_serial_per_sec / bsp_get_serial_rate;
diff --git a/c/src/lib/libcpu/powerpc/ppc403/console/console405.c b/c/src/lib/libcpu/powerpc/ppc403/console/console405.c
index 5e8a3b25eb..ef8ff2db15 100644
--- a/c/src/lib/libcpu/powerpc/ppc403/console/console405.c
+++ b/c/src/lib/libcpu/powerpc/ppc403/console/console405.c
@@ -367,14 +367,14 @@ spiInitialize(void)
    * Select clock source and set uart internal clock divisor
    */
 
-  asm volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */
+  __asm__ volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */
 
   /* UART0 bit 24 0x80, UART1 bit 25 0x40 */
   tmp |= (bsp_serial_external_clock ?  (USE_UART ? 0x40 : 0x80) : 0);
 
   tmp |= (bsp_serial_external_clock ?  0: ((UART_INTERNAL_CLOCK_DIVISOR -1) << 1));
 
-  asm volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/
+  __asm__ volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/
 
   /* Disable port interrupts while changing hardware */
   _ier = port->IER;
diff --git a/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c b/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c
index 86558485e4..eacfbb8e06 100644
--- a/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c
+++ b/c/src/lib/libcpu/powerpc/ppc403/irq/ictrl.c
@@ -47,7 +47,7 @@ rtems_isr_entry ictrl_vector_table[PPC_IRQ_EXT_MAX];
 RTEMS_INLINE_ROUTINE void
 clr_exisr(uint32_t   mask)
 {
-    asm volatile ("mtdcr 0xC0,%0"::"r" (mask));/*EXISR*/
+    __asm__ volatile ("mtdcr 0xC0,%0"::"r" (mask));/*EXISR*/
 }
 
 /*
@@ -58,7 +58,7 @@ get_exisr(void)
 {
     uint32_t   val;
 
-    asm volatile ("mfdcr %0,0xC0":"=r" (val));/*EXISR*/
+    __asm__ volatile ("mfdcr %0,0xC0":"=r" (val));/*EXISR*/
     return val;
 }
 
@@ -69,7 +69,7 @@ RTEMS_INLINE_ROUTINE uint32_t
 get_exier(void)
 {
     uint32_t   val;
-    asm volatile ("mfdcr %0,0xC2":"=r" (val));/*EXIER*/
+    __asm__ volatile ("mfdcr %0,0xC2":"=r" (val));/*EXIER*/
     return val;
 }
 
@@ -79,7 +79,7 @@ get_exier(void)
 RTEMS_INLINE_ROUTINE void
 set_exier(uint32_t   val)
 {
-    asm volatile ("mtdcr 0xC2,%0"::"r" (val));/*EXIER*/
+    __asm__ volatile ("mtdcr 0xC2,%0"::"r" (val));/*EXIER*/
 }
 
 #else /* not ppc405 */
@@ -87,7 +87,7 @@ set_exier(uint32_t   val)
 RTEMS_INLINE_ROUTINE void
 clr_exisr(uint32_t   mask)
 {
-    asm volatile ("mtdcr 0x40,%0"::"r" (mask));/*EXISR*/
+    __asm__ volatile ("mtdcr 0x40,%0"::"r" (mask));/*EXISR*/
 }
 
 /*
@@ -98,7 +98,7 @@ get_exisr(void)
 {
     uint32_t   val;
 
-    asm volatile ("mfdcr %0,0x40":"=r" (val));/*EXISR*/
+    __asm__ volatile ("mfdcr %0,0x40":"=r" (val));/*EXISR*/
     return val;
 }
 
@@ -109,7 +109,7 @@ RTEMS_INLINE_ROUTINE uint32_t
 get_exier(void)
 {
     uint32_t   val;
-    asm volatile ("mfdcr %0,0x42":"=r" (val));/*EXIER*/
+    __asm__ volatile ("mfdcr %0,0x42":"=r" (val));/*EXIER*/
     return val;
 }
 
@@ -119,7 +119,7 @@ get_exier(void)
 RTEMS_INLINE_ROUTINE void
 set_exier(uint32_t   val)
 {
-    asm volatile ("mtdcr 0x42,%0"::"r" (val));/*EXIER*/
+    __asm__ volatile ("mtdcr 0x42,%0"::"r" (val));/*EXIER*/
 }
 #endif /* ppc405 */
 /*
diff --git a/c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c b/c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c
index 5bcfc2ac77..7a52950285 100644
--- a/c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c
+++ b/c/src/lib/libcpu/powerpc/ppc403/tty_drv/tty_drv.c
@@ -359,14 +359,14 @@ tty0Initialize(void)
    * Select clock source and set uart internal clock divisor
    */
 
-  asm volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */
+  __asm__ volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */
 
   /* UART0 bit 24 0x80, UART1 bit 25 0x40 */
   tmp |= (bsp_serial_external_clock ?  (TTY0_USE_UART ? 0x40 : 0x80) : 0);
 
   tmp |= (bsp_serial_external_clock ?  0: ((TTY0_UART_INTERNAL_CLOCK_DIVISOR -1) << 1));
 
-  asm volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/
+  __asm__ volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/
 
   /* Disable tty0port interrupts while changing hardware */
   _ier = tty0port->IER;
diff --git a/c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h b/c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h
index 6cdc9c6ee0..00383fb44c 100644
--- a/c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h
+++ b/c/src/lib/libcpu/powerpc/rtems/powerpc/cache.h
@@ -13,7 +13,7 @@
 #define _CPU_Data_Cache_Block_Flush( _address ) \
   do { register void *__address = (_address); \
        register uint32_t   _zero = 0; \
-       asm volatile ( "dcbf %0,%1" : \
+       __asm__ volatile ( "dcbf %0,%1" : \
 		      "=r" (_zero), "=r" (__address) : \
                       "0" (_zero), "1" (__address) \
        ); \
@@ -29,7 +29,7 @@
 #define _CPU_Data_Cache_Block_Invalidate( _address ) \
   do { register void *__address = (_address); \
        register uint32_t   _zero = 0; \
-       asm volatile ( "dcbi %0,%1" : \
+       __asm__ volatile ( "dcbi %0,%1" : \
 		      "=r" (_zero), "=r" (__address) : \
                       "0" (_zero), "1" (__address) \
        ); \
diff --git a/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h b/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h
index 68e16b1c52..2d8f9b38e9 100644
--- a/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h
+++ b/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h
@@ -57,7 +57,7 @@ static inline uint8_t ppc_read_byte(const volatile void *src)
 {
   uint8_t value;
 
-  asm volatile (
+  __asm__ volatile (
     "lbz %0, 0(%1)"
     : "=r" (value)
     : "b" (src)
@@ -73,7 +73,7 @@ static inline uint16_t ppc_read_half_word(const volatile void *src)
 {
   uint16_t value;
 
-  asm volatile (
+  __asm__ volatile (
     "lhz %0, 0(%1)"
     : "=r" (value)
     : "b" (src)
@@ -89,7 +89,7 @@ static inline uint32_t ppc_read_word(const volatile void *src)
 {
   uint32_t value;
 
-  asm volatile (
+  __asm__ volatile (
     "lwz %0, 0(%1)"
     : "=r" (value)
     : "b" (src)
@@ -103,7 +103,7 @@ static inline uint32_t ppc_read_word(const volatile void *src)
  */
 static inline void ppc_write_byte(uint8_t value, volatile void *dest)
 {
-  asm volatile (
+  __asm__ volatile (
     "stb %0, 0(%1)"
     :
     : "r" (value), "b" (dest)
@@ -115,7 +115,7 @@ static inline void ppc_write_byte(uint8_t value, volatile void *dest)
  */
 static inline void ppc_write_half_word(uint16_t value, volatile void *dest)
 {
-  asm volatile (
+  __asm__ volatile (
     "sth %0, 0(%1)"
     :
     : "r" (value), "b" (dest)
@@ -127,7 +127,7 @@ static inline void ppc_write_half_word(uint16_t value, volatile void *dest)
  */
 static inline void ppc_write_word(uint32_t value, volatile void *dest)
 {
-  asm volatile (
+  __asm__ volatile (
     "stw %0, 0(%1)" :
     : "r" (value), "b" (dest)
   );
@@ -138,7 +138,7 @@ static inline void *ppc_stack_pointer(void)
 {
   void *sp;
 
-  asm volatile (
+  __asm__ volatile (
     "mr %0, 1"
     : "=r" (sp)
   );
@@ -148,7 +148,7 @@ static inline void *ppc_stack_pointer(void)
 
 static inline void ppc_set_stack_pointer(void *sp)
 {
-  asm volatile (
+  __asm__ volatile (
     "mr 1, %0"
     :
     : "r" (sp)
@@ -159,7 +159,7 @@ static inline void *ppc_link_register(void)
 {
   void *lr;
 
-  asm volatile (
+  __asm__ volatile (
     "mflr %0"
     : "=r" (lr)
   );
@@ -169,7 +169,7 @@ static inline void *ppc_link_register(void)
 
 static inline void ppc_set_link_register(void *lr)
 {
-  asm volatile (
+  __asm__ volatile (
     "mtlr %0"
     :
     : "r" (lr)
@@ -180,7 +180,7 @@ static inline uint32_t ppc_machine_state_register(void)
 {
   uint32_t msr;
 
-  asm volatile (
+  __asm__ volatile (
     "mfmsr %0"
     : "=r" (msr)
   );
@@ -190,7 +190,7 @@ static inline uint32_t ppc_machine_state_register(void)
 
 static inline void ppc_set_machine_state_register(uint32_t msr)
 {
-  asm volatile (
+  __asm__ volatile (
     "mtmsr %0"
     :
     : "r" (msr)
@@ -201,14 +201,14 @@ static inline void ppc_synchronize_data(void)
 {
   RTEMS_COMPILER_MEMORY_BARRIER();
 
-  asm volatile ("sync");
+  __asm__ volatile ("sync");
 }
 
 static inline void ppc_synchronize_instructions(void)
 {
   RTEMS_COMPILER_MEMORY_BARRIER();
 
-  asm volatile ("isync");
+  __asm__ volatile ("isync");
 }
 
 /**
@@ -224,7 +224,7 @@ static inline uint32_t ppc_external_exceptions_enable(void)
 
   RTEMS_COMPILER_MEMORY_BARRIER();
 
-  asm volatile (
+  __asm__ volatile (
     "mfmsr %0;"
     "ori %1, %0, 0x8000;"
     "mtmsr %1"
@@ -266,10 +266,10 @@ static inline void ppc_external_exceptions_disable(uint32_t msr)
  * 2009/10/30 Th. D.
  */
 #define CPU_Get_timebase_low( _value ) \
-    asm volatile( "mftb  %0" : "=r" (_value) )
+    __asm__ volatile( "mftb  %0" : "=r" (_value) )
 #else
 #define CPU_Get_timebase_low( _value ) \
-    asm volatile( "mfspr %0,268" : "=r" (_value) )
+    __asm__ volatile( "mfspr %0,268" : "=r" (_value) )
 #endif
 
 /* Must be provided for rtems_bsp_delay to work */
@@ -300,11 +300,11 @@ extern     uint32_t bsp_clicks_per_usec;
 
 #define PPC_Set_decrementer( _clicks ) \
   do { \
-    asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \
+    __asm__ volatile( "mtdec %0" : : "r" ((_clicks)) ); \
   } while (0)
 
 #define PPC_Get_decrementer( _clicks ) \
-    asm volatile( "mfdec  %0" : "=r" (_clicks) )
+    __asm__ volatile( "mfdec  %0" : "=r" (_clicks) )
 
 /*
  *  Routines to access the time base register
@@ -320,13 +320,13 @@ static inline uint64_t PPC_Get_timebase_register( void )
   do {
 #if defined(mpx8xx) || defined(mpc860) || defined(mpc821)
 /* See comment above (CPU_Get_timebase_low) */
-    asm volatile( "mftbu %0" : "=r" (tbr_high_old));
-    asm volatile( "mftb  %0" : "=r" (tbr_low));
-    asm volatile( "mftbu %0" : "=r" (tbr_high));
+    __asm__ volatile( "mftbu %0" : "=r" (tbr_high_old));
+    __asm__ volatile( "mftb  %0" : "=r" (tbr_low));
+    __asm__ volatile( "mftbu %0" : "=r" (tbr_high));
 #else
-    asm volatile( "mfspr %0, 269" : "=r" (tbr_high_old));
-    asm volatile( "mfspr %0, 268" : "=r" (tbr_low));
-    asm volatile( "mfspr %0, 269" : "=r" (tbr_high));
+    __asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high_old));
+    __asm__ volatile( "mfspr %0, 268" : "=r" (tbr_low));
+    __asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high));
 #endif
   } while ( tbr_high_old != tbr_high );
 
@@ -343,8 +343,8 @@ static inline  void PPC_Set_timebase_register (uint64_t tbr)
 
   tbr_low = (uint32_t) tbr;
   tbr_high = (uint32_t) (tbr >> 32);
-  asm volatile( "mtspr 284, %0" : : "r" (tbr_low));
-  asm volatile( "mtspr 285, %0" : : "r" (tbr_high));
+  __asm__ volatile( "mtspr 284, %0" : : "r" (tbr_low));
+  __asm__ volatile( "mtspr 285, %0" : : "r" (tbr_high));
 
 }
 
@@ -375,7 +375,7 @@ static inline void ppc_set_decrementer_register(uint32_t dec)
 #define PPC_SPECIAL_PURPOSE_REGISTER(spr) \
   ({ \
     uint32_t val; \
-    asm volatile (\
+    __asm__ volatile (\
       "mfspr %0, " PPC_STRINGOF(spr) \
       : "=r" (val) \
     ); \
@@ -388,7 +388,7 @@ static inline void ppc_set_decrementer_register(uint32_t dec)
  */
 #define PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val) \
   do { \
-    asm volatile (\
+    __asm__ volatile (\
       "mtspr " PPC_STRINGOF(spr) ", %0" \
       : \
       : "r" (val) \
@@ -462,7 +462,7 @@ static inline void ppc_set_decrementer_register(uint32_t dec)
 #define PPC_DEVICE_CONTROL_REGISTER(dcr) \
   ({ \
     uint32_t val; \
-    asm volatile (\
+    __asm__ volatile (\
       "mfdcr %0, " PPC_STRINGOF(dcr) \
       : "=r" (val) \
     ); \
@@ -477,7 +477,7 @@ static inline void ppc_set_decrementer_register(uint32_t dec)
  */
 #define PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val) \
   do { \
-    asm volatile (\
+    __asm__ volatile (\
       "mtdcr " PPC_STRINGOF(dcr) ", %0" \
       : \
       : "r" (val) \
diff --git a/c/src/lib/libcpu/powerpc/shared/src/cache.c b/c/src/lib/libcpu/powerpc/shared/src/cache.c
index d40e7d0f39..00d16924a9 100644
--- a/c/src/lib/libcpu/powerpc/shared/src/cache.c
+++ b/c/src/lib/libcpu/powerpc/shared/src/cache.c
@@ -33,7 +33,7 @@
 #define PPC_Get_HID0( _value ) \
   do { \
       _value = 0;        /* to avoid warnings */ \
-      asm volatile( \
+      __asm__ volatile( \
           "mfspr %0, 0x3f0;"     /* get HID0 */ \
           "isync" \
           : "=r" (_value) \
@@ -43,7 +43,7 @@
 
 #define PPC_Set_HID0( _value ) \
   do { \
-      asm volatile( \
+      __asm__ volatile( \
           "isync;" \
           "mtspr 0x3f0, %0;"     /* load HID0 */ \
           "isync" \
@@ -269,14 +269,14 @@ void _CPU_cache_invalidate_1_data_line(
 	const void * _address )
 {
   register const void *__address = _address;
-  asm volatile ( "dcbi 0,%0" :: "r"(__address) : "memory" );
+  __asm__ volatile ( "dcbi 0,%0" :: "r"(__address) : "memory" );
 }
 
 void _CPU_cache_flush_1_data_line(
 	const void * _address )
 {
   register const void *__address = _address;
-  asm volatile ( "dcbf 0,%0" :: "r" (__address) : "memory" );
+  __asm__ volatile ( "dcbf 0,%0" :: "r" (__address) : "memory" );
 }
 
 
@@ -284,7 +284,7 @@ void _CPU_cache_invalidate_1_instruction_line(
 	const void * _address )
 {
   register const void *__address = _address;
-  asm volatile ( "icbi 0,%0" :: "r" (__address) : "memory");
+  __asm__ volatile ( "icbi 0,%0" :: "r" (__address) : "memory");
 }
 
 /* end of file */