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authorSebastian Huber <sebastian.huber@embedded-brains.de>2016-12-02 13:10:31 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2016-12-02 13:11:13 +0100
commitf65dcc712ab7ff1fb36da4254b4383f4fc5eb459 (patch)
treea37c212885e27376d7a5718d2fdf1b4f5c9e9e89
parentrtems: Use _Thread_Dispatch_direct() (diff)
downloadrtems-f65dcc712ab7ff1fb36da4254b4383f4fc5eb459.tar.bz2
score: Fix ARM and PowerPC context initialization
Update #2751.
-rw-r--r--c/src/lib/libcpu/powerpc/new-exceptions/cpu.c1
-rw-r--r--cpukit/score/cpu/arm/cpu.c1
-rw-r--r--cpukit/score/cpu/no_cpu/rtems/score/cpu.h4
3 files changed, 6 insertions, 0 deletions
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c b/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c
index 1e564f77e6..71dce73eab 100644
--- a/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c
+++ b/c/src/lib/libcpu/powerpc/new-exceptions/cpu.c
@@ -118,6 +118,7 @@ void _CPU_Context_Initialize(
the_ppc_context->gpr1 = sp;
the_ppc_context->msr = msr_value;
the_ppc_context->lr = (uint32_t) entry_point;
+ the_ppc_context->isr_dispatch_disable = 0;
#if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC)
_CPU_Context_initialize_altivec( the_ppc_context );
diff --git a/cpukit/score/cpu/arm/cpu.c b/cpukit/score/cpu/arm/cpu.c
index dc87844483..b5738b11f4 100644
--- a/cpukit/score/cpu/arm/cpu.c
+++ b/cpukit/score/cpu/arm/cpu.c
@@ -109,6 +109,7 @@ void _CPU_Context_Initialize(
the_context->register_lr = (uint32_t) entry_point;
the_context->register_cpsr = ( ( new_level != 0 ) ? ARM_PSR_I : 0 )
| arm_cpu_mode;
+ the_context->isr_dispatch_disable = 0;
#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
the_context->thread_id = (uint32_t) tls_area;
diff --git a/cpukit/score/cpu/no_cpu/rtems/score/cpu.h b/cpukit/score/cpu/no_cpu/rtems/score/cpu.h
index 58a024ef0c..56081477d9 100644
--- a/cpukit/score/cpu/no_cpu/rtems/score/cpu.h
+++ b/cpukit/score/cpu/no_cpu/rtems/score/cpu.h
@@ -872,6 +872,10 @@ uint32_t _CPU_ISR_Get_level( void );
* in the context. The state of the "general data" registers is
* undefined at task start time.
*
+ * The ISR dispatch disable field of the context must be cleared to zero if it
+ * is used by the CPU port. Otherwise, a thread restart results in
+ * unpredictable behaviour.
+ *
* @param[in] _the_context is the context structure to be initialized
* @param[in] _stack_base is the lowest physical address of this task's stack
* @param[in] _size is the size of this task's stack