diff options
| author | Ralf Kirchner <ralf.kirchner@embedded-brains.de> | 2013-10-16 10:39:05 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-03-13 16:10:52 +0100 |
| commit | f5c106456c7a897f82cba84d57fa031bb0221859 (patch) | |
| tree | 87f60811fd80397c948ffe67a1cb08afe934264f | |
| parent | bsp/arm: SMP support for a9mpcore_clock_cleanup() (diff) | |
| download | rtems-f5c106456c7a897f82cba84d57fa031bb0221859.tar.bz2 | |
bsp/arm: Invalidate SCU
| -rw-r--r-- | c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h | 12 | ||||
| -rw-r--r-- | c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h | 14 |
2 files changed, 25 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h index 0910e4c5b2..28640d2a42 100644 --- a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h +++ b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h @@ -46,6 +46,18 @@ typedef struct { #define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) uint32_t pwrst; uint32_t invss; +#define A9MPCORE_SCU_INVSS_CPU0(ways) BSP_FLD32(val, 0, 3) +#define A9MPCORE_SCU_INVSS_CPU0_GET(reg) /* Write only register */ +#define A9MPCORE_SCU_INVSS_CPU0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) +#define A9MPCORE_SCU_INVSS_CPU1(ways) BSP_FLD32(val, 4, 7) +#define A9MPCORE_SCU_INVSS_CPU1_GET(reg) /* Write only register */ +#define A9MPCORE_SCU_INVSS_CPU1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) +#define A9MPCORE_SCU_INVSS_CPU2(ways) BSP_FLD32(val, 8, 11) +#define A9MPCORE_SCU_INVSS_CPU2_GET(reg) /* Write only register */ +#define A9MPCORE_SCU_INVSS_CPU2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) +#define A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15) +#define A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */ +#define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) uint32_t reserved_10[12]; uint32_t fltstart; uint32_t fltend; diff --git a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h index dd1b7c1499..c89ca9d643 100644 --- a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h +++ b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. * * embedded brains GmbH * Dornierstr. 4 @@ -70,6 +70,15 @@ BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_set_vector_base(void) } } +BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_scu_invalidate( + volatile a9mpcore_scu *scu, + uint32_t cpu_id, + uint32_t ways +) +{ + scu->invss = (ways & 0xf) << ((cpu_id & 0x3) * 4); +} + BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_0(void) { #ifdef RTEMS_SMP @@ -86,6 +95,9 @@ BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_0(void) arm_cp15_set_auxiliary_control(actlr); cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id(); + + arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xf); + if (cpu_id != 0) { arm_a9mpcore_start_set_vector_base(); |