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authorJoel Sherrill <joel.sherrill@OARcorp.com>2003-07-18 17:24:48 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2003-07-18 17:24:48 +0000
commitec821afa54ae27926a08bc49a855add0cb493e13 (patch)
treeaf06e6df7b776a4781a8ac77c09f9f2daf0c7a7e
parent2003-07-18 Till Straumann <strauman@slac.stanford.edu> (diff)
downloadrtems-ec821afa54ae27926a08bc49a855add0cb493e13.tar.bz2
2003-07-18 Till Straumann <strauman@slac.stanford.edu>
PR 288/rtems * irq/irq_asm.S, startup/bspstart.c: _ISR_Nest_level is now properly maintained and any BSP which does not do so will trip a panic in the shared code.
-rw-r--r--c/src/lib/libbsp/powerpc/shared/ChangeLog7
-rw-r--r--c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S27
-rw-r--r--c/src/lib/libbsp/powerpc/shared/startup/bspstart.c13
3 files changed, 40 insertions, 7 deletions
diff --git a/c/src/lib/libbsp/powerpc/shared/ChangeLog b/c/src/lib/libbsp/powerpc/shared/ChangeLog
index 4f315b5c94..0dfe4bfc5c 100644
--- a/c/src/lib/libbsp/powerpc/shared/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/shared/ChangeLog
@@ -1,5 +1,12 @@
2003-07-18 Till Straumann <strauman@slac.stanford.edu>
+ PR 288/rtems
+ * irq/irq_asm.S, startup/bspstart.c: _ISR_Nest_level is now properly
+ maintained and any BSP which does not do so will trip a panic in the
+ shared code.
+
+2003-07-18 Till Straumann <strauman@slac.stanford.edu>
+
PR 415/bsps
* pci/detect_raven_bridge.c, startup/bspstart.c:
This patch reverts enabling MCP interrupts for the motorola_powerpc
diff --git a/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S b/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S
index ad01722742..cf396d3279 100644
--- a/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S
+++ b/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S
@@ -9,6 +9,9 @@
* Modified to support the MCP750.
* Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
*
+ * Till Straumann <strauman@slac.stanford.edu>, 2003/7:
+ * - store isr nesting level in _ISR_Nest_level rather than
+ * SPRG0 - RTEMS relies on that variable.
*
* $Id$
*/
@@ -140,10 +143,18 @@ SYM (shared_raw_irq_code_entry):
* store part of _Thread_Dispatch_disable_level address in R15
*/
addis r15,0, _Thread_Dispatch_disable_level@ha
+#if BROKEN_ISR_NEST_LEVEL
/*
* Get current nesting level in R3
*/
mfspr r3, SPRG0
+#else
+ /*
+ * Retrieve current nesting level from _ISR_Nest_level
+ */
+ lis r7, _ISR_Nest_level@ha
+ lwz r3, _ISR_Nest_level@l(r7)
+#endif
/*
* Check if stack switch is necessary
*/
@@ -160,10 +171,15 @@ nested:
* Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level
*/
lwz r6,_Thread_Dispatch_disable_level@l(r15)
+#if BROKEN_ISR_NEST_LEVEL
/*
- * store new nesting level in SPRG0
+ * Store new nesting level in SPRG0
*/
mtspr SPRG0, r3
+#else
+ /* store new nesting level in _ISR_Nest_level */
+ stw r3, _ISR_Nest_level@l(r7)
+#endif
addi r6, r6, 1
mfmsr r5
@@ -187,14 +203,23 @@ nested:
* value as an easy exit condition because if interrupt nesting level > 1
* then _Thread_Dispatch_disable_level > 1
*/
+#if BROKEN_ISR_NEST_LEVEL
mfspr r4, SPRG0
+#else
+ lis r7, _ISR_Nest_level@ha
+ lwz r4, _ISR_Nest_level@l(r7)
+#endif
/*
* start decrementing _Thread_Dispatch_disable_level
*/
lwz r3,_Thread_Dispatch_disable_level@l(r15)
addi r4, r4, -1 /* Continue decrementing nesting level */
addi r3, r3, -1 /* Continue decrementing _Thread_Dispatch_disable_level */
+#if BROKEN_ISR_NEST_LEVEL
mtspr SPRG0, r4 /* End decrementing nesting level */
+#else
+ stw r4, _ISR_Nest_level@l(r7) /* End decrementing nesting level */
+#endif
stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
cmpwi r3, 0
/*
diff --git a/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c b/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c
index dce5fb6191..2ee9c53cb1 100644
--- a/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c
@@ -45,8 +45,8 @@ extern Triv121PgTbl BSP_pgtbl_setup();
extern void BSP_pgtbl_activate();
extern void BSP_vme_config();
-SPR_RW(SPR0)
-SPR_RW(SPR1)
+SPR_RW(SPRG0)
+SPR_RW(SPRG1)
/*
* Copy of residuals passed by firmware
@@ -179,7 +179,6 @@ void bsp_start( void )
unsigned char *stack;
unsigned l2cr;
register unsigned char* intrStack;
- register unsigned int intrNestingLevel = 0;
unsigned char *work_space_start;
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
@@ -219,7 +218,6 @@ void bsp_start( void )
/*
* Initialize the interrupt related settings
- * SPRG0 = interrupt nesting level count
* SPRG1 = software managed IRQ stack
*
* This could be done latter (e.g in IRQ_INIT) but it helps to understand
@@ -233,8 +231,11 @@ void bsp_start( void )
/* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
*((unsigned32 *)intrStack) = 0;
- _write_SPR1((unsigned int)intrStack);
- _write_SPR0(intrNestingLevel);
+ _write_SPRG1((unsigned int)intrStack);
+
+ /* signal them that we have fixed PR288 - eventually, this should go away */
+ _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
+
/*
* Initialize default raw exception hanlders. See vectors/vectors_init.c
*/