Changes to reflect new revision of erc32 per Jiri Gaisler's suggestions.

This is current as of sis 2.6.

8 files changed, 77 insertions, 38 deletions

diff --git a/c/src/exec/score/cpu/sparc/asm.h b/c/src/exec/score/cpu/sparc/asm.h
index a3d62416b8..4f425de956 100644
--- a/c/src/exec/score/cpu/sparc/asm.h
+++ b/c/src/exec/score/cpu/sparc/asm.h
@@ -105,6 +105,16 @@
   jmp   %l4+%lo(_handler); \
   mov   _vector, %l3
 
+/*
+ *  Used for the reset trap for ERC32 to avoid a supervisor instruction
+ */
+ 
+#define RTRAP(_vector, _handler)  \
+  mov   %g0, %l0 ; \
+  sethi %hi(_handler), %l4 ; \
+  jmp   %l4+%lo(_handler); \
+  mov   _vector, %l3
+
 #endif
 /* end of include file */
 
diff --git a/c/src/exec/score/cpu/sparc/cpu.c b/c/src/exec/score/cpu/sparc/cpu.c
index 23a93f176e..54344192c8 100644
--- a/c/src/exec/score/cpu/sparc/cpu.c
+++ b/c/src/exec/score/cpu/sparc/cpu.c
@@ -65,6 +65,8 @@ void _CPU_Initialize(
 )
 {
   void                  *pointer;
+
+#ifndef NO_TABLE_MOVE
   unsigned32             trap_table_start;
   unsigned32             tbr_value;
   CPU_Trap_table_entry  *old_tbr;
@@ -77,6 +79,7 @@ void _CPU_Initialize(
    *  and overflow handlers.  It is the responsibility of the BSP to provide
    *  install these in the initial trap table.
    */
+
  
   trap_table_start = (unsigned32) &_CPU_Trap_Table_area;
   if (trap_table_start & (SPARC_TRAP_TABLE_ALIGNMENT-1))
@@ -93,6 +96,8 @@ void _CPU_Initialize(
 
   sparc_set_tbr( trap_table_start );
 
+#endif
+
   /*
    *  This seems to be the most appropriate way to obtain an initial
    *  FP context on the SPARC.  The NULL fp context is copied it to
diff --git a/c/src/exec/score/cpu/sparc/cpu.h b/c/src/exec/score/cpu/sparc/cpu.h
index 0571ba5bd0..fe849c79d0 100644
--- a/c/src/exec/score/cpu/sparc/cpu.h
+++ b/c/src/exec/score/cpu/sparc/cpu.h
@@ -585,8 +585,11 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
  
 #define SPARC_TRAP_TABLE_ALIGNMENT 4096
  
+#ifndef NO_TABLE_MOVE
+
 SCORE_EXTERN unsigned8 _CPU_Trap_Table_area[ 8192 ]
            __attribute__ ((aligned (SPARC_TRAP_TABLE_ALIGNMENT)));
+#endif
  
 
 /*
diff --git a/c/src/exec/score/cpu/sparc/erc32.h b/c/src/exec/score/cpu/sparc/erc32.h
index 16d5e3d476..47050054ba 100644
--- a/c/src/exec/score/cpu/sparc/erc32.h
+++ b/c/src/exec/score/cpu/sparc/erc32.h
@@ -242,14 +242,14 @@ typedef struct {
 #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB  ( 7 << 10 )
 
 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK  0x001C0000
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4K    ( 0 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8K    ( 1 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16K   ( 2 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_32K   ( 3 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_64K   ( 4 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K  ( 5 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K  ( 6 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K  ( 7 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K    ( 0 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K    ( 1 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K   ( 2 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M   ( 3 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M   ( 4 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M  ( 5 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M  ( 6 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M  ( 7 << 18 )
  
 /*
  *  The following defines the bits in the Timer Control Register.
@@ -276,15 +276,9 @@ typedef struct {
 /*
  *  The following defines the bits in the UART Control Registers.
  *
- *  NOTE: Same bits in UART channels A and B.
  */
 
 #define ERC32_MEC_UART_CONTROL_RTD  0x000000FF /* RX/TX data */ 
-#define ERC32_MEC_UART_CONTROL_DR   0x00000100 /* RX Data Ready */
-#define ERC32_MEC_UART_CONTROL_TSE  0x00000200 /* TX Send Empty */
-                                               /*   (i.e. no data to send) */
-#define ERC32_MEC_UART_CONTROL_THE  0x00000400 /* TX Hold Empty */
-                                               /*   (i.e. ready to load) */
  
 /*
  *  The following defines the bits in the MEC UART Control Registers.
@@ -298,6 +292,10 @@ typedef struct {
 #define ERC32_MEC_UART_STATUS_OE   0x00000040 /* RX Overrun Error */
 #define ERC32_MEC_UART_STATUS_CU   0x00000080 /* Clear Errors */
 #define ERC32_MEC_UART_STATUS_TXE  0x00000006 /* TX Empty */
+#define ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */
+#define ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */
+#define ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */
+#define ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */
 
 #define ERC32_MEC_UART_STATUS_DRA   (ERC32_MEC_UART_STATUS_DR  << 0)
 #define ERC32_MEC_UART_STATUS_TSEA  (ERC32_MEC_UART_STATUS_TSE << 0)
@@ -349,8 +347,8 @@ extern ERC32_Register_Map ERC32_MEC;
     \
     sparc_disable_interrupts( _level ); \
     ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \
-    sparc_enable_interrupts( _level ); \
     ERC32_MEC.Interrupt_Force = (1 << (_source)); \
+    sparc_enable_interrupts( _level ); \
   } while (0)
  
 #define ERC32_Is_interrupt_pending( _source ) \
@@ -469,7 +467,7 @@ extern unsigned32 _ERC32_MEC_Timer_Control_Mirror;
     sparc_disable_interrupts( _level ); \
       _control = _ERC32_MEC_Timer_Control_Mirror; \
       _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \
-      _ERC32_MEC_Timer_Control_Mirror = _control | __value; \
+      _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
       _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \
       _control |= __value; \
       /* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control );  */ \
@@ -479,7 +477,7 @@ extern unsigned32 _ERC32_MEC_Timer_Control_Mirror;
 
 #define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \
   do { \
-    (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
+    (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
   } while ( 0 )
 
 /*
@@ -498,7 +496,7 @@ extern unsigned32 _ERC32_MEC_Timer_Control_Mirror;
     sparc_disable_interrupts( _level ); \
       _control = _ERC32_MEC_Timer_Control_Mirror; \
       _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \
-      _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
+      _ERC32_MEC_Timer_Control_Mirror = _control | __value; \
       _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \
       _control |= __value; \
       /* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \
@@ -508,7 +506,7 @@ extern unsigned32 _ERC32_MEC_Timer_Control_Mirror;
  
 #define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \
   do { \
-    (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
+    (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
   } while ( 0 )
 
 
diff --git a/c/src/lib/libcpu/sparc/include/erc32.h b/c/src/lib/libcpu/sparc/include/erc32.h
index 16d5e3d476..47050054ba 100644
--- a/c/src/lib/libcpu/sparc/include/erc32.h
+++ b/c/src/lib/libcpu/sparc/include/erc32.h
@@ -242,14 +242,14 @@ typedef struct {
 #define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB  ( 7 << 10 )
 
 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK  0x001C0000
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4K    ( 0 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8K    ( 1 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16K   ( 2 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_32K   ( 3 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_64K   ( 4 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K  ( 5 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K  ( 6 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K  ( 7 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K    ( 0 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K    ( 1 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K   ( 2 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M   ( 3 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M   ( 4 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M  ( 5 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M  ( 6 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M  ( 7 << 18 )
  
 /*
  *  The following defines the bits in the Timer Control Register.
@@ -276,15 +276,9 @@ typedef struct {
 /*
  *  The following defines the bits in the UART Control Registers.
  *
- *  NOTE: Same bits in UART channels A and B.
  */
 
 #define ERC32_MEC_UART_CONTROL_RTD  0x000000FF /* RX/TX data */ 
-#define ERC32_MEC_UART_CONTROL_DR   0x00000100 /* RX Data Ready */
-#define ERC32_MEC_UART_CONTROL_TSE  0x00000200 /* TX Send Empty */
-                                               /*   (i.e. no data to send) */
-#define ERC32_MEC_UART_CONTROL_THE  0x00000400 /* TX Hold Empty */
-                                               /*   (i.e. ready to load) */
  
 /*
  *  The following defines the bits in the MEC UART Control Registers.
@@ -298,6 +292,10 @@ typedef struct {
 #define ERC32_MEC_UART_STATUS_OE   0x00000040 /* RX Overrun Error */
 #define ERC32_MEC_UART_STATUS_CU   0x00000080 /* Clear Errors */
 #define ERC32_MEC_UART_STATUS_TXE  0x00000006 /* TX Empty */
+#define ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */
+#define ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */
+#define ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */
+#define ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */
 
 #define ERC32_MEC_UART_STATUS_DRA   (ERC32_MEC_UART_STATUS_DR  << 0)
 #define ERC32_MEC_UART_STATUS_TSEA  (ERC32_MEC_UART_STATUS_TSE << 0)
@@ -349,8 +347,8 @@ extern ERC32_Register_Map ERC32_MEC;
     \
     sparc_disable_interrupts( _level ); \
     ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \
-    sparc_enable_interrupts( _level ); \
     ERC32_MEC.Interrupt_Force = (1 << (_source)); \
+    sparc_enable_interrupts( _level ); \
   } while (0)
  
 #define ERC32_Is_interrupt_pending( _source ) \
@@ -469,7 +467,7 @@ extern unsigned32 _ERC32_MEC_Timer_Control_Mirror;
     sparc_disable_interrupts( _level ); \
       _control = _ERC32_MEC_Timer_Control_Mirror; \
       _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \
-      _ERC32_MEC_Timer_Control_Mirror = _control | __value; \
+      _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
       _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \
       _control |= __value; \
       /* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control );  */ \
@@ -479,7 +477,7 @@ extern unsigned32 _ERC32_MEC_Timer_Control_Mirror;
 
 #define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \
   do { \
-    (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
+    (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
   } while ( 0 )
 
 /*
@@ -498,7 +496,7 @@ extern unsigned32 _ERC32_MEC_Timer_Control_Mirror;
     sparc_disable_interrupts( _level ); \
       _control = _ERC32_MEC_Timer_Control_Mirror; \
       _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \
-      _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
+      _ERC32_MEC_Timer_Control_Mirror = _control | __value; \
       _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \
       _control |= __value; \
       /* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \
@@ -508,7 +506,7 @@ extern unsigned32 _ERC32_MEC_Timer_Control_Mirror;
  
 #define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \
   do { \
-    (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
+    (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
   } while ( 0 )
 
 
diff --git a/cpukit/score/cpu/sparc/asm.h b/cpukit/score/cpu/sparc/asm.h
index a3d62416b8..4f425de956 100644
--- a/cpukit/score/cpu/sparc/asm.h
+++ b/cpukit/score/cpu/sparc/asm.h
@@ -105,6 +105,16 @@
   jmp   %l4+%lo(_handler); \
   mov   _vector, %l3
 
+/*
+ *  Used for the reset trap for ERC32 to avoid a supervisor instruction
+ */
+ 
+#define RTRAP(_vector, _handler)  \
+  mov   %g0, %l0 ; \
+  sethi %hi(_handler), %l4 ; \
+  jmp   %l4+%lo(_handler); \
+  mov   _vector, %l3
+
 #endif
 /* end of include file */
 
diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c
index 23a93f176e..54344192c8 100644
--- a/cpukit/score/cpu/sparc/cpu.c
+++ b/cpukit/score/cpu/sparc/cpu.c
@@ -65,6 +65,8 @@ void _CPU_Initialize(
 )
 {
   void                  *pointer;
+
+#ifndef NO_TABLE_MOVE
   unsigned32             trap_table_start;
   unsigned32             tbr_value;
   CPU_Trap_table_entry  *old_tbr;
@@ -77,6 +79,7 @@ void _CPU_Initialize(
    *  and overflow handlers.  It is the responsibility of the BSP to provide
    *  install these in the initial trap table.
    */
+
  
   trap_table_start = (unsigned32) &_CPU_Trap_Table_area;
   if (trap_table_start & (SPARC_TRAP_TABLE_ALIGNMENT-1))
@@ -93,6 +96,8 @@ void _CPU_Initialize(
 
   sparc_set_tbr( trap_table_start );
 
+#endif
+
   /*
    *  This seems to be the most appropriate way to obtain an initial
    *  FP context on the SPARC.  The NULL fp context is copied it to
diff --git a/cpukit/score/cpu/sparc/rtems/asm.h b/cpukit/score/cpu/sparc/rtems/asm.h
index a3d62416b8..4f425de956 100644
--- a/cpukit/score/cpu/sparc/rtems/asm.h
+++ b/cpukit/score/cpu/sparc/rtems/asm.h
@@ -105,6 +105,16 @@
   jmp   %l4+%lo(_handler); \
   mov   _vector, %l3
 
+/*
+ *  Used for the reset trap for ERC32 to avoid a supervisor instruction
+ */
+ 
+#define RTRAP(_vector, _handler)  \
+  mov   %g0, %l0 ; \
+  sethi %hi(_handler), %l4 ; \
+  jmp   %l4+%lo(_handler); \
+  mov   _vector, %l3
+
 #endif
 /* end of include file */