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| author | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2009-03-19 10:49:55 +0000 |
|---|---|---|
| committer | Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> | 2009-03-19 10:49:55 +0000 |
| commit | ce7d6e62b78ab7ee7ad35498c7735dd782d56d59 (patch) | |
| tree | f6d9687bbdd72eca81749fa570ba8dceffa1a61c | |
| parent | 2009-03-12 Santosh G Vattam <vattam.santosh@gmail.com> (diff) | |
| download | rtems-ce7d6e62b78ab7ee7ad35498c7735dd782d56d59.tar.bz2 | |
* start/start.S, include/hwreg_vals.h, startup/cpuinit.c:
correct some init values for HSC_CM01 boards
| -rw-r--r-- | c/src/lib/libbsp/powerpc/gen83xx/ChangeLog | 5 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h | 14 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/gen83xx/start/start.S | 13 | ||||
| -rw-r--r-- | c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c | 2 |
4 files changed, 25 insertions, 9 deletions
diff --git a/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog b/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog index 072ad94e2f..b2d5adbc00 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog +++ b/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog @@ -1,3 +1,8 @@ +2009-03-18 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> + + * start/start.S, include/hwreg_vals.h, startup/cpuinit.c: + correct some init values for HSC_CM01 boards + 2009-02-12 Joel Sherrill <joel.sherrill@oarcorp.com> * startup/bspstart.c: Change prototype of IDLE thread to consistently diff --git a/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h index 34c20f53e6..7c43be8832 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h +++ b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h @@ -207,26 +207,26 @@ #define LBLAWBAR0_VAL bsp_rom_start #define LBLAWAR0_VAL 0x80000018 #define LBLAWBAR1_VAL (FPGA_CONFIG_START) -#define LBLAWAR1_VAL 0x80000015 +#define LBLAWAR1_VAL 0x80000018 #define DDRLAWBAR0_VAL bsp_ram_start #define DDRLAWAR0_VAL 0x8000001B /* * Local Bus (Memory) Controller * FIXME: decode bit settings */ -#define BR0_VAL 0xFE001001 +#define BR0_VAL (0xFE000000 | 0x01001) #define OR0_VAL 0xFE000E54 // fpga config access range (UPM_A) (32 kByte) #define BR2_VAL (FPGA_CONFIG_START | 0x01881) -#define OR2_VAL 0xFFF80100 +#define OR2_VAL 0xFFFF9100 // fpga register access range (UPM_B) (8 MByte) #define BR3_VAL (FPGA_REGISTER_START | 0x018A1) -#define OR3_VAL 0xFF800100 +#define OR3_VAL 0xFF801100 -// fpga fifo access range (UPM_B) (8 MByte) -#define BR4_VAL (FPGA_FIFO_START | 0x018A1) -#define OR4_VAL 0xFF800100 +// fpga fifo access range (UPM_C) (8 MByte) +#define BR4_VAL (FPGA_FIFO_START | 0x018C1) +#define OR4_VAL 0xFF801100 /* * SDRAM registers diff --git a/c/src/lib/libbsp/powerpc/gen83xx/start/start.S b/c/src/lib/libbsp/powerpc/gen83xx/start/start.S index 86a9c33b51..bf4a2e4851 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/start/start.S +++ b/c/src/lib/libbsp/powerpc/gen83xx/start/start.S @@ -199,7 +199,18 @@ start_code_in_rom: #ifdef OR3_VAL SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL #endif - +#ifdef BR4_VAL + SET_IMM_REGW r31,r30,BR4_OFF,BR4_VAL +#endif +#ifdef OR4_VAL + SET_IMM_REGW r31,r30,OR4_OFF,OR4_VAL +#endif +#ifdef BR5_VAL + SET_IMM_REGW r31,r30,BR5_OFF,BR5_VAL +#endif +#ifdef OR5_VAL + SET_IMM_REGW r31,r30,OR5_OFF,OR5_VAL +#endif /* * ROM startup: init SDRAM access window */ diff --git a/c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c b/c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c index 6cfa7fc02b..d3f04d26c7 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c +++ b/c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c @@ -235,7 +235,7 @@ void cpu_init( void) (uint32_t) bsp_rom_start, (uint32_t) bsp_rom_size, #endif /* HAS_UBOOT */ - false, + true, false, false, false, |