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authorRalf Corsepius <ralf.corsepius@rtems.org>2004-03-30 11:49:14 +0000
committerRalf Corsepius <ralf.corsepius@rtems.org>2004-03-30 11:49:14 +0000
commitc346f33d6df5aba8e1ce76d61a2357529ab6e353 (patch)
tree899d3710bf2cb2831cdd2bf45e7421e3ac76e0b4
parente6aeabd8dcc7c34a66bd2b688f836be2eb847111 (diff)
downloadrtems-c346f33d6df5aba8e1ce76d61a2357529ab6e353.tar.bz2
2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>
* cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
Diffstat (limited to '')
-rw-r--r--cpukit/score/cpu/arm/ChangeLog4
-rw-r--r--cpukit/score/cpu/arm/cpu.c40
-rw-r--r--cpukit/score/cpu/arm/rtems/score/cpu.h64
-rw-r--r--cpukit/score/cpu/h8300/ChangeLog4
-rw-r--r--cpukit/score/cpu/h8300/cpu.c6
-rw-r--r--cpukit/score/cpu/h8300/rtems/score/cpu.h46
-rw-r--r--cpukit/score/cpu/i960/ChangeLog4
-rw-r--r--cpukit/score/cpu/i960/cpu.c6
-rw-r--r--cpukit/score/cpu/i960/rtems/score/cpu.h62
-rw-r--r--cpukit/score/cpu/mips/ChangeLog4
-rw-r--r--cpukit/score/cpu/mips/cpu.c8
-rw-r--r--cpukit/score/cpu/mips/rtems/score/cpu.h38
-rw-r--r--cpukit/score/cpu/no_cpu/ChangeLog4
-rw-r--r--cpukit/score/cpu/no_cpu/cpu.c6
-rw-r--r--cpukit/score/cpu/no_cpu/rtems/score/cpu.h22
-rw-r--r--cpukit/score/cpu/unix/ChangeLog4
-rw-r--r--cpukit/score/cpu/unix/cpu.c62
-rw-r--r--cpukit/score/cpu/unix/rtems/score/cpu.h38
18 files changed, 223 insertions, 199 deletions
diff --git a/cpukit/score/cpu/arm/ChangeLog b/cpukit/score/cpu/arm/ChangeLog
index 39182a3857..63ac7378b6 100644
--- a/cpukit/score/cpu/arm/ChangeLog
+++ b/cpukit/score/cpu/arm/ChangeLog
@@ -1,3 +1,7 @@
+2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>
+
+ * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
+
2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org>
* configure.ac: RTEMS_TOP([../../../..]).
diff --git a/cpukit/score/cpu/arm/cpu.c b/cpukit/score/cpu/arm/cpu.c
index d95be8e5bb..a546e9692a 100644
--- a/cpukit/score/cpu/arm/cpu.c
+++ b/cpukit/score/cpu/arm/cpu.c
@@ -32,8 +32,8 @@
*
*/
-unsigned32 g_data_abort_cnt = 0;
-unsigned32 g_data_abort_insn_list[1024];
+uint32_t g_data_abort_cnt = 0;
+uint32_t g_data_abort_insn_list[1024];
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
@@ -48,9 +48,9 @@ void _CPU_Initialize(
* _CPU_ISR_Get_level - returns the current interrupt level
*/
-unsigned32 _CPU_ISR_Get_level( void )
+uint32_t _CPU_ISR_Get_level( void )
{
- unsigned32 reg = 0; /* to avoid warning */
+ uint32_t reg = 0; /* to avoid warning */
asm volatile ("mrs %0, cpsr \n" \
"and %0, %0, #0xc0 \n" \
@@ -80,7 +80,7 @@ unsigned32 _CPU_ISR_Get_level( void )
*
*/
void _CPU_ISR_install_vector(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
@@ -98,15 +98,15 @@ void _CPU_ISR_install_vector(
void _CPU_Context_Initialize(
Context_Control *the_context,
- unsigned32 *stack_base,
- unsigned32 size,
- unsigned32 new_level,
+ uint32_t *stack_base,
+ uint32_t size,
+ uint32_t new_level,
void *entry_point,
boolean is_fp
)
{
- the_context->register_sp = (unsigned32)stack_base + size ;
- the_context->register_lr = (unsigned32)entry_point;
+ the_context->register_sp = (uint32_t )stack_base + size ;
+ the_context->register_lr = (uint32_t )entry_point;
the_context->register_cpsr = new_level | 0x13;
}
@@ -217,8 +217,8 @@ void rtems_exception_init_mngt()
#define GET_U(x) ((x & 0x00800000) >> 23)
#define GET_I(x) ((x & 0x02000000) >> 25)
-#define GET_REG(r, ctx) (((unsigned32 *)ctx)[r])
-#define SET_REG(r, ctx, v) (((unsigned32 *)ctx)[r] = v)
+#define GET_REG(r, ctx) (((uint32_t *)ctx)[r])
+#define SET_REG(r, ctx, v) (((uint32_t *)ctx)[r] = v)
#define GET_OFFSET(insn) (insn & 0xfff)
@@ -228,17 +228,17 @@ void rtems_exception_init_mngt()
* All unhandled instructions cause the system to hang.
*/
-void do_data_abort(unsigned32 insn, unsigned32 spsr,
+void do_data_abort(uint32_t insn, uint32_t spsr,
CPU_Exception_frame *ctx)
{
- unsigned8 decode;
- unsigned8 insn_type;
+ uint8_t decode;
+ uint8_t insn_type;
- unsigned32 rn;
- unsigned32 rd;
+ uint32_t rn;
+ uint32_t rd;
- unsigned8 *src_addr;
- unsigned32 tmp;
+ uint8_t *src_addr;
+ uint32_t tmp;
g_data_abort_insn_list[g_data_abort_cnt & 0x3ff] = ctx->register_lr - 8;
g_data_abort_cnt++;
@@ -281,7 +281,7 @@ void do_data_abort(unsigned32 insn, unsigned32 spsr,
printk("\tUser mode\n");
break;
case 0x10: /* P=1, W=0 -> base not updated */
- src_addr = (unsigned8 *)GET_REG(rn, ctx);
+ src_addr = (uint8_t *)GET_REG(rn, ctx);
if (GET_U(insn) == 0) {
src_addr -= GET_OFFSET(insn);
} else {
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h
index f23db2eded..4c69a35561 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpu.h
@@ -334,18 +334,18 @@ extern "C" {
* a debugger such as gdb. But that is another problem.
*/
typedef struct {
- unsigned32 register_cpsr;
- unsigned32 register_r4;
- unsigned32 register_r5;
- unsigned32 register_r6;
- unsigned32 register_r7;
- unsigned32 register_r8;
- unsigned32 register_r9;
- unsigned32 register_r10;
- unsigned32 register_fp;
- unsigned32 register_sp;
- unsigned32 register_lr;
- unsigned32 register_pc;
+ uint32_t register_cpsr;
+ uint32_t register_r4;
+ uint32_t register_r5;
+ uint32_t register_r6;
+ uint32_t register_r7;
+ uint32_t register_r8;
+ uint32_t register_r9;
+ uint32_t register_r10;
+ uint32_t register_fp;
+ uint32_t register_sp;
+ uint32_t register_lr;
+ uint32_t register_pc;
} Context_Control;
typedef struct {
@@ -353,12 +353,12 @@ typedef struct {
} Context_Control_fp;
typedef struct {
- unsigned32 register_r0;
- unsigned32 register_r1;
- unsigned32 register_r2;
- unsigned32 register_r3;
- unsigned32 register_ip;
- unsigned32 register_lr;
+ uint32_t register_r0;
+ uint32_t register_r1;
+ uint32_t register_r2;
+ uint32_t register_r3;
+ uint32_t register_ip;
+ uint32_t register_lr;
} CPU_Exception_frame;
typedef void (*cpuExcHandlerType) (CPU_Exception_frame*);
@@ -384,10 +384,10 @@ typedef struct {
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
- unsigned32 idle_task_stack_size;
- unsigned32 interrupt_stack_size;
- unsigned32 extra_mpci_receive_server_stack;
- void * (*stack_allocate_hook)( unsigned32 );
+ uint32_t idle_task_stack_size;
+ uint32_t interrupt_stack_size;
+ uint32_t extra_mpci_receive_server_stack;
+ void * (*stack_allocate_hook)( uint32_t );
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
@@ -576,7 +576,7 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
}
-unsigned32 _CPU_ISR_Get_level( void );
+uint32_t _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
@@ -605,9 +605,9 @@ unsigned32 _CPU_ISR_Get_level( void );
void _CPU_Context_Initialize(
Context_Control *the_context,
- unsigned32 *stack_base,
- unsigned32 size,
- unsigned32 new_level,
+ uint32_t *stack_base,
+ uint32_t size,
+ uint32_t new_level,
void *entry_point,
boolean is_fp
);
@@ -812,7 +812,7 @@ typedef enum {
*/
void _CPU_ISR_install_vector(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
@@ -898,7 +898,7 @@ static inline unsigned int CPU_swap_u32(
unsigned int value
)
{
- unsigned32 tmp = value; /* make compiler warnings go away */
+ uint32_t tmp = value; /* make compiler warnings go away */
asm volatile ("EOR %1, %0, %0, ROR #16\n"
"BIC %1, %1, #0xff0000\n"
"MOV %0, %0, ROR #8\n"
@@ -909,12 +909,12 @@ static inline unsigned int CPU_swap_u32(
return value;
}
-static inline unsigned16 CPU_swap_u16(unsigned16 value)
+static inline uint16_t CPU_swap_u16(uint16_t value)
{
- unsigned16 lower;
- unsigned16 upper;
+ uint16_t lower;
+ uint16_t upper;
- value = value & (unsigned16) 0xffff;
+ value = value & (uint16_t ) 0xffff;
lower = (value >> 8) ;
upper = (value << 8) ;
diff --git a/cpukit/score/cpu/h8300/ChangeLog b/cpukit/score/cpu/h8300/ChangeLog
index a04a7759d0..8615f81197 100644
--- a/cpukit/score/cpu/h8300/ChangeLog
+++ b/cpukit/score/cpu/h8300/ChangeLog
@@ -1,3 +1,7 @@
+2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>
+
+ * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
+
2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org>
* configure.ac: RTEMS_TOP([../../../..]).
diff --git a/cpukit/score/cpu/h8300/cpu.c b/cpukit/score/cpu/h8300/cpu.c
index 91586c9594..f49978bb55 100644
--- a/cpukit/score/cpu/h8300/cpu.c
+++ b/cpukit/score/cpu/h8300/cpu.c
@@ -62,7 +62,7 @@ void _CPU_Initialize(
* This routine returns the current interrupt level.
*/
-unsigned32 _CPU_ISR_Get_level( void )
+uint32_t _CPU_ISR_Get_level( void )
{
unsigned int _ccr;
@@ -83,7 +83,7 @@ unsigned32 _CPU_ISR_Get_level( void )
*/
void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
@@ -113,7 +113,7 @@ void _CPU_ISR_install_raw_handler(
*/
void _CPU_ISR_install_vector(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
diff --git a/cpukit/score/cpu/h8300/rtems/score/cpu.h b/cpukit/score/cpu/h8300/rtems/score/cpu.h
index d7abc15b5f..1f80c36f78 100644
--- a/cpukit/score/cpu/h8300/rtems/score/cpu.h
+++ b/cpukit/score/cpu/h8300/rtems/score/cpu.h
@@ -378,16 +378,16 @@ extern "C" {
#define nogap __attribute__ ((packed))
typedef struct {
- unsigned16 ccr nogap;
+ uint16_t ccr nogap;
void *er7 nogap;
void *er6 nogap;
- unsigned32 er5 nogap;
- unsigned32 er4 nogap;
- unsigned32 er3 nogap;
- unsigned32 er2 nogap;
- unsigned32 er1 nogap;
- unsigned32 er0 nogap;
- unsigned32 xxx nogap;
+ uint32_t er5 nogap;
+ uint32_t er4 nogap;
+ uint32_t er3 nogap;
+ uint32_t er2 nogap;
+ uint32_t er1 nogap;
+ uint32_t er0 nogap;
+ uint32_t xxx nogap;
} Context_Control;
typedef struct {
@@ -395,7 +395,7 @@ typedef struct {
} Context_Control_fp;
typedef struct {
- unsigned32 special_interrupt_register;
+ uint32_t special_interrupt_register;
} CPU_Interrupt_frame;
@@ -420,10 +420,10 @@ typedef struct {
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
- unsigned32 idle_task_stack_size;
- unsigned32 interrupt_stack_size;
- unsigned32 extra_mpci_receive_server_stack;
- void * (*stack_allocate_hook)( unsigned32 );
+ uint32_t idle_task_stack_size;
+ uint32_t interrupt_stack_size;
+ uint32_t extra_mpci_receive_server_stack;
+ void * (*stack_allocate_hook)( uint32_t );
void (*stack_free_hook)( void* );
} rtems_cpu_table;
@@ -614,7 +614,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
#define _CPU_Initialize_vectors()
/* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools.
- Note requires ISR_Level be unsigned16 or assembler croaks.
+ Note requires ISR_Level be uint16_t or assembler croaks.
*/
#if (__GNUC__ == 2 && __GNUC_MINOR__ == 7 )
@@ -748,7 +748,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
else asm volatile ( "andc #0x7f,ccr\n" ); \
}
-unsigned32 _CPU_ISR_Get_level( void );
+uint32_t _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
@@ -787,12 +787,12 @@ unsigned32 _CPU_ISR_Get_level( void );
_isr, _entry_point, _is_fp ) \
/* Locate Me */ \
do { \
- unsigned32 _stack; \
+ uint32_t _stack; \
\
if ( (_isr) ) (_the_context)->ccr = CPU_CCR_INTERRUPTS_OFF; \
else (_the_context)->ccr = CPU_CCR_INTERRUPTS_ON; \
\
- _stack = ((unsigned32)(_stack_base)) + (_size) - 4; \
+ _stack = ((uint32_t )(_stack_base)) + (_size) - 4; \
*((proc_ptr *)(_stack)) = (_entry_point); \
(_the_context)->er7 = (void *) _stack; \
(_the_context)->er6 = (void *) _stack; \
@@ -1023,7 +1023,7 @@ void _CPU_Initialize(
*/
void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
@@ -1039,7 +1039,7 @@ void _CPU_ISR_install_raw_handler(
*/
void _CPU_ISR_install_vector(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
@@ -1158,11 +1158,11 @@ void _CPU_Context_restore_fp(
* This is the generic implementation.
*/
-static inline unsigned32 CPU_swap_u32(
- unsigned32 value
+static inline uint32_t CPU_swap_u32(
+ uint32_t value
)
{
- unsigned32 byte1, byte2, byte3, byte4, swapped;
+ uint32_t byte1, byte2, byte3, byte4, swapped;
byte4 = (value >> 24) & 0xff;
byte3 = (value >> 16) & 0xff;
@@ -1178,7 +1178,7 @@ static inline unsigned32 CPU_swap_u32(
/* to be provided by the BSP */
extern void H8BD_Install_IRQ(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler );
diff --git a/cpukit/score/cpu/i960/ChangeLog b/cpukit/score/cpu/i960/ChangeLog
index c2ac4c280c..2e8a37927a 100644
--- a/cpukit/score/cpu/i960/ChangeLog
+++ b/cpukit/score/cpu/i960/ChangeLog
@@ -1,3 +1,7 @@
+2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>
+
+ * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
+
2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org>
* configure.ac: RTEMS_TOP([../../../..]).
diff --git a/cpukit/score/cpu/i960/cpu.c b/cpukit/score/cpu/i960/cpu.c
index dbe1002880..5a26da446f 100644
--- a/cpukit/score/cpu/i960/cpu.c
+++ b/cpukit/score/cpu/i960/cpu.c
@@ -41,9 +41,9 @@ void _CPU_Initialize(
* _CPU_ISR_Get_level
*/
-unsigned32 _CPU_ISR_Get_level( void )
+uint32_t _CPU_ISR_Get_level( void )
{
- unsigned32 level;
+ uint32_t level;
i960_get_interrupt_level( level );
@@ -66,7 +66,7 @@ unsigned32 _CPU_ISR_Get_level( void )
*/
void _CPU_ISR_install_vector(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
diff --git a/cpukit/score/cpu/i960/rtems/score/cpu.h b/cpukit/score/cpu/i960/rtems/score/cpu.h
index 01ef426dd6..77a6dc55a6 100644
--- a/cpukit/score/cpu/i960/rtems/score/cpu.h
+++ b/cpukit/score/cpu/i960/rtems/score/cpu.h
@@ -87,14 +87,14 @@ extern "C" {
typedef struct {
void *r0_pfp; /* (r0) Previous Frame Pointer */
void *r1_sp; /* (r1) Stack Pointer */
- unsigned32 pc; /* (pc) Processor Control */
+ uint32_t pc; /* (pc) Processor Control */
void *g8; /* (g8) Global Register 8 */
void *g9; /* (g9) Global Register 9 */
void *g10; /* (g10) Global Register 10 */
void *g11; /* (g11) Global Register 11 */
void *g12; /* (g12) Global Register 12 */
void *g13; /* (g13) Global Register 13 */
- unsigned32 g14; /* (g14) Global Register 14 */
+ uint32_t g14; /* (g14) Global Register 14 */
void *g15_fp; /* (g15) Frame Pointer */
} Context_Control;
@@ -103,18 +103,18 @@ typedef struct {
*/
typedef struct {
- unsigned32 fp0_1; /* (fp0) first word */
- unsigned32 fp0_2; /* (fp0) second word */
- unsigned32 fp0_3; /* (fp0) third word */
- unsigned32 fp1_1; /* (fp1) first word */
- unsigned32 fp1_2; /* (fp1) second word */
- unsigned32 fp1_3; /* (fp1) third word */
- unsigned32 fp2_1; /* (fp2) first word */
- unsigned32 fp2_2; /* (fp2) second word */
- unsigned32 fp2_3; /* (fp2) third word */
- unsigned32 fp3_1; /* (fp3) first word */
- unsigned32 fp3_2; /* (fp3) second word */
- unsigned32 fp3_3; /* (fp3) third word */
+ uint32_t fp0_1; /* (fp0) first word */
+ uint32_t fp0_2; /* (fp0) second word */
+ uint32_t fp0_3; /* (fp0) third word */
+ uint32_t fp1_1; /* (fp1) first word */
+ uint32_t fp1_2; /* (fp1) second word */
+ uint32_t fp1_3; /* (fp1) third word */
+ uint32_t fp2_1; /* (fp2) first word */
+ uint32_t fp2_2; /* (fp2) second word */
+ uint32_t fp2_3; /* (fp2) third word */
+ uint32_t fp3_1; /* (fp3) first word */
+ uint32_t fp3_2; /* (fp3) second word */
+ uint32_t fp3_3; /* (fp3) third word */
} Context_Control_fp;
/*
@@ -123,7 +123,7 @@ typedef struct {
*/
typedef struct {
- unsigned32 TBD; /* XXX Fix for this CPU */
+ uint32_t TBD; /* XXX Fix for this CPU */
} CPU_Interrupt_frame;
/*
@@ -161,10 +161,10 @@ typedef struct {
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
- unsigned32 idle_task_stack_size;
- unsigned32 interrupt_stack_size;
- unsigned32 extra_mpci_receive_server_stack;
- void * (*stack_allocate_hook)( unsigned32 );
+ uint32_t idle_task_stack_size;
+ uint32_t interrupt_stack_size;
+ uint32_t extra_mpci_receive_server_stack;
+ void * (*stack_allocate_hook)( uint32_t );
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
} rtems_cpu_table;
@@ -267,8 +267,8 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
#define _CPU_ISR_Set_level( newlevel ) \
{ \
- unsigned32 _mask = 0; \
- unsigned32 _level = (newlevel); \
+ uint32_t _mask = 0; \
+ uint32_t _level = (newlevel); \
\
__asm__ volatile ( "ldconst 0x1f0000,%0; \
modpc 0,%0,%1" : "=d" (_mask), "=d" (_level) \
@@ -276,7 +276,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
); \
}
-unsigned32 _CPU_ISR_Get_level( void );
+uint32_t _CPU_ISR_Get_level( void );
/* ISR handler section macros */
@@ -293,12 +293,12 @@ unsigned32 _CPU_ISR_Get_level( void );
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
_isr, _entry, _is_fp ) \
{ CPU_Call_frame *_texit_frame; \
- unsigned32 _mask; \
- unsigned32 _base_pc; \
- unsigned32 _stack_tmp; \
+ uint32_t _mask; \
+ uint32_t _base_pc; \
+ uint32_t _stack_tmp; \
void *_stack; \
\
- _stack_tmp = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \
+ _stack_tmp = (uint32_t )(_stack_base) + CPU_STACK_ALIGNMENT; \
_stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
_stack = (void *) _stack_tmp; \
\
@@ -337,8 +337,8 @@ unsigned32 _CPU_ISR_Get_level( void );
*/
#define _CPU_Fatal_halt( _errorcode ) \
- { unsigned32 _mask, _level; \
- unsigned32 _error = (_errorcode); \
+ { uint32_t _mask, _level; \
+ uint32_t _error = (_errorcode); \
\
__asm__ volatile ( "ldconst 0x1f0000,%0 ; \
mov %0,%1 ; \
@@ -361,7 +361,7 @@ unsigned32 _CPU_ISR_Get_level( void );
#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
- { unsigned32 _search = (_value); \
+ { uint32_t _search = (_value); \
\
(_output) = 0; /* to prevent warnings */ \
__asm__ volatile ( "scanbit %0,%1 " \
@@ -410,7 +410,7 @@ void _CPU_Initialize(
*/
void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
@@ -422,7 +422,7 @@ void _CPU_ISR_install_raw_handler(
*/
void _CPU_ISR_install_vector(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
diff --git a/cpukit/score/cpu/mips/ChangeLog b/cpukit/score/cpu/mips/ChangeLog
index df578dc0a2..20f3d62564 100644
--- a/cpukit/score/cpu/mips/ChangeLog
+++ b/cpukit/score/cpu/mips/ChangeLog
@@ -1,3 +1,7 @@
+2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>
+
+ * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
+
2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org>
* configure.ac: RTEMS_TOP([../../../..]).
diff --git a/cpukit/score/cpu/mips/cpu.c b/cpukit/score/cpu/mips/cpu.c
index 4b525d5544..50904f9371 100644
--- a/cpukit/score/cpu/mips/cpu.c
+++ b/cpukit/score/cpu/mips/cpu.c
@@ -93,7 +93,7 @@ void _CPU_Initialize(
* This routine returns the current interrupt level.
*/
-unsigned32 _CPU_ISR_Get_level( void )
+uint32_t _CPU_ISR_Get_level( void )
{
unsigned int sr;
@@ -117,7 +117,7 @@ unsigned32 _CPU_ISR_Get_level( void )
}
-void _CPU_ISR_Set_level( unsigned32 new_level )
+void _CPU_ISR_Set_level( uint32_t new_level )
{
unsigned int sr, srbits;
@@ -185,7 +185,7 @@ void _CPU_ISR_Set_level( unsigned32 new_level )
*/
void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
@@ -216,7 +216,7 @@ void _CPU_ISR_install_raw_handler(
*/
void _CPU_ISR_install_vector(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h
index ba6a16572e..a829d32254 100644
--- a/cpukit/score/cpu/mips/rtems/score/cpu.h
+++ b/cpukit/score/cpu/mips/rtems/score/cpu.h
@@ -357,11 +357,11 @@ extern "C" {
/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
#if __mips == 1
-#define __MIPS_REGISTER_TYPE unsigned32
-#define __MIPS_FPU_REGISTER_TYPE unsigned32
+#define __MIPS_REGISTER_TYPE uint32_t
+#define __MIPS_FPU_REGISTER_TYPE uint32_t
#elif __mips == 3
-#define __MIPS_REGISTER_TYPE unsigned64
-#define __MIPS_FPU_REGISTER_TYPE unsigned64
+#define __MIPS_REGISTER_TYPE uint64_t
+#define __MIPS_FPU_REGISTER_TYPE uint64_t
#else
#error "mips register size: unknown architecture level!!"
#endif
@@ -581,14 +581,14 @@ typedef struct {
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
- unsigned32 idle_task_stack_size;
- unsigned32 interrupt_stack_size;
- unsigned32 extra_mpci_receive_server_stack;
- void * (*stack_allocate_hook)( unsigned32 );
+ uint32_t idle_task_stack_size;
+ uint32_t interrupt_stack_size;
+ uint32_t extra_mpci_receive_server_stack;
+ void * (*stack_allocate_hook)( uint32_t );
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
- unsigned32 clicks_per_microsecond;
+ uint32_t clicks_per_microsecond;
} rtems_cpu_table;
@@ -683,7 +683,7 @@ extern unsigned int mips_interrupt_number_of_vectors;
* that a "reasonable" small application should not have any problems.
*/
-#define CPU_STACK_MINIMUM_SIZE (2048*sizeof(unsigned32))
+#define CPU_STACK_MINIMUM_SIZE (2048*sizeof(uint32_t ))
/*
@@ -797,9 +797,9 @@ extern unsigned int mips_interrupt_number_of_vectors;
* manipulates the IEC.
*/
-unsigned32 _CPU_ISR_Get_level( void ); /* in cpu.c */
+uint32_t _CPU_ISR_Get_level( void ); /* in cpu.c */
-void _CPU_ISR_Set_level( unsigned32 ); /* in cpu.c */
+void _CPU_ISR_Set_level( uint32_t ); /* in cpu.c */
/* end of ISR handler macros */
@@ -857,13 +857,13 @@ void _CPU_ISR_Set_level( unsigned32 ); /* in cpu.c */
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, _isr, _entry_point, _is_fp ) \
{ \
- unsigned32 _stack_tmp = \
- (unsigned32)(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \
- unsigned32 _intlvl = _isr & 0xff; \
+ uint32_t _stack_tmp = \
+ (uint32_t )(_stack_base) + (_size) - CPU_STACK_ALIGNMENT; \
+ uint32_t _intlvl = _isr & 0xff; \
_stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
(_the_context)->sp = _stack_tmp; \
(_the_context)->fp = _stack_tmp; \
- (_the_context)->ra = (unsigned64)_entry_point; \
+ (_the_context)->ra = (uint64_t )_entry_point; \
(_the_context)->c0_sr = ((_intlvl==0)?(0xFF00 | _INTON):( ((_intlvl<<9) & 0xfc00) | \
0x300 | \
((_intlvl & 1)?_INTON:0)) ) | \
@@ -1062,7 +1062,7 @@ void _CPU_Initialize(
*/
void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
@@ -1074,7 +1074,7 @@ void _CPU_ISR_install_raw_handler(
*/
void _CPU_ISR_install_vector(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
@@ -1169,7 +1169,7 @@ static inline unsigned int CPU_swap_u32(
unsigned int value
)
{
- unsigned32 byte1, byte2, byte3, byte4, swapped;
+ uint32_t byte1, byte2, byte3, byte4, swapped;
byte4 = (value >> 24) & 0xff;
byte3 = (value >> 16) & 0xff;
diff --git a/cpukit/score/cpu/no_cpu/ChangeLog b/cpukit/score/cpu/no_cpu/ChangeLog
index d533be20a5..0faae64834 100644
--- a/cpukit/score/cpu/no_cpu/ChangeLog
+++ b/cpukit/score/cpu/no_cpu/ChangeLog
@@ -1,3 +1,7 @@
+2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>
+
+ * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
+
2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org>
* configure.ac: RTEMS_TOP([../../../..]).
diff --git a/cpukit/score/cpu/no_cpu/cpu.c b/cpukit/score/cpu/no_cpu/cpu.c
index 5ddc34e2ad..2796c707ea 100644
--- a/cpukit/score/cpu/no_cpu/cpu.c
+++ b/cpukit/score/cpu/no_cpu/cpu.c
@@ -69,7 +69,7 @@ void _CPU_Initialize(
* XXX document implementation including references if appropriate
*/
-unsigned32 _CPU_ISR_Get_level( void )
+uint32_t _CPU_ISR_Get_level( void )
{
/*
* This routine returns the current interrupt level.
@@ -88,7 +88,7 @@ unsigned32 _CPU_ISR_Get_level( void )
*/
void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
@@ -120,7 +120,7 @@ void _CPU_ISR_install_raw_handler(
*/
void _CPU_ISR_install_vector(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
diff --git a/cpukit/score/cpu/no_cpu/rtems/score/cpu.h b/cpukit/score/cpu/no_cpu/rtems/score/cpu.h
index a40e8863a6..55534f7182 100644
--- a/cpukit/score/cpu/no_cpu/rtems/score/cpu.h
+++ b/cpukit/score/cpu/no_cpu/rtems/score/cpu.h
@@ -408,8 +408,8 @@ extern "C" {
*/
typedef struct {
- unsigned32 some_integer_register;
- unsigned32 some_system_register;
+ uint32_t some_integer_register;
+ uint32_t some_system_register;
} Context_Control;
typedef struct {
@@ -417,7 +417,7 @@ typedef struct {
} Context_Control_fp;
typedef struct {
- unsigned32 special_interrupt_register;
+ uint32_t special_interrupt_register;
} CPU_Interrupt_frame;
@@ -436,10 +436,10 @@ typedef struct {
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
- unsigned32 idle_task_stack_size;
- unsigned32 interrupt_stack_size;
- unsigned32 extra_mpci_receive_server_stack;
- void * (*stack_allocate_hook)( unsigned32 );
+ uint32_t idle_task_stack_size;
+ uint32_t interrupt_stack_size;
+ uint32_t extra_mpci_receive_server_stack;
+ void * (*stack_allocate_hook)( uint32_t );
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
@@ -726,7 +726,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
{ \
}
-unsigned32 _CPU_ISR_Get_level( void );
+uint32_t _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
@@ -982,7 +982,7 @@ void _CPU_Initialize(
*/
void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
@@ -998,7 +998,7 @@ void _CPU_ISR_install_raw_handler(
*/
void _CPU_ISR_install_vector(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
@@ -1121,7 +1121,7 @@ static inline unsigned int CPU_swap_u32(
unsigned int value
)
{
- unsigned32 byte1, byte2, byte3, byte4, swapped;
+ uint32_t byte1, byte2, byte3, byte4, swapped;
byte4 = (value >> 24) & 0xff;
byte3 = (value >> 16) & 0xff;
diff --git a/cpukit/score/cpu/unix/ChangeLog b/cpukit/score/cpu/unix/ChangeLog
index 5bd201514f..b0954559fc 100644
--- a/cpukit/score/cpu/unix/ChangeLog
+++ b/cpukit/score/cpu/unix/ChangeLog
@@ -1,3 +1,7 @@
+2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>
+
+ * cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
+
2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org>
* configure.ac: RTEMS_TOP([../../../..]).
diff --git a/cpukit/score/cpu/unix/cpu.c b/cpukit/score/cpu/unix/cpu.c
index 3984a5d833..c0c700fab6 100644
--- a/cpukit/score/cpu/unix/cpu.c
+++ b/cpukit/score/cpu/unix/cpu.c
@@ -86,7 +86,7 @@ sigset_t posix_empty_mask;
void _CPU_Initialize_vectors(void)
{
- unsigned32 i;
+ uint32_t i;
proc_ptr old_handler;
/*
@@ -194,7 +194,7 @@ void _CPU_Context_From_CPU_Init()
*/
{
- extern unsigned32 _SYSTEM_ID;
+ extern uint32_t _SYSTEM_ID;
_SYSTEM_ID = 0x20c;
}
@@ -254,7 +254,7 @@ void _CPU_Sync_io_Init()
* _CPU_ISR_Get_level
*/
-unsigned32 _CPU_ISR_Get_level( void )
+uint32_t _CPU_ISR_Get_level( void )
{
sigset_t old_mask;
@@ -327,7 +327,7 @@ void _CPU_Initialize(
*/
void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
@@ -353,7 +353,7 @@ void _CPU_ISR_install_raw_handler(
void _CPU_ISR_install_vector(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
@@ -460,20 +460,20 @@ void _CPU_Thread_Idle_body( void )
void _CPU_Context_Initialize(
Context_Control *_the_context,
- unsigned32 *_stack_base,
- unsigned32 _size,
- unsigned32 _new_level,
+ uint32_t *_stack_base,
+ uint32_t _size,
+ uint32_t _new_level,
void *_entry_point,
boolean _is_fp
)
{
- unsigned32 *addr;
- unsigned32 jmp_addr;
- unsigned32 _stack_low; /* lowest "stack aligned" address */
- unsigned32 _stack_high; /* highest "stack aligned" address */
- unsigned32 _the_size;
+ uint32_t *addr;
+ uint32_t jmp_addr;
+ uint32_t _stack_low; /* lowest "stack aligned" address */
+ uint32_t _stack_high; /* highest "stack aligned" address */
+ uint32_t _the_size;
- jmp_addr = (unsigned32) _entry_point;
+ jmp_addr = (uint32_t ) _entry_point;
/*
* On CPUs with stacks which grow down, we build the stack
@@ -481,10 +481,10 @@ void _CPU_Context_Initialize(
* grow up, we build the stack based on the _stack_low address.
*/
- _stack_low = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT - 1;
+ _stack_low = (uint32_t )(_stack_base) + CPU_STACK_ALIGNMENT - 1;
_stack_low &= ~(CPU_STACK_ALIGNMENT - 1);
- _stack_high = (unsigned32)(_stack_base) + _size;
+ _stack_high = (uint32_t )(_stack_base) + _size;
_stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
if (_stack_high > _stack_low)
@@ -503,11 +503,11 @@ void _CPU_Context_Initialize(
*(Context_Control_overlay *)_the_context =
_CPU_Context_Default_with_ISRs_disabled;
- addr = (unsigned32 *)_the_context;
+ addr = (uint32_t *)_the_context;
#if defined(__hppa__)
*(addr + RP_OFF) = jmp_addr;
- *(addr + SP_OFF) = (unsigned32)(_stack_low + CPU_FRAME_SIZE);
+ *(addr + SP_OFF) = (uint32_t )(_stack_low + CPU_FRAME_SIZE);
/*
* See if we are using shared libraries by checking
@@ -518,7 +518,7 @@ void _CPU_Context_Initialize(
if (jmp_addr & 0x40000000) {
jmp_addr &= 0xfffffffc;
- *(addr + RP_OFF) = *(unsigned32 *)jmp_addr;
+ *(addr + RP_OFF) = *(uint32_t *)jmp_addr;
}
#elif defined(__sparc__)
@@ -530,8 +530,8 @@ void _CPU_Context_Initialize(
asm ("ta 0x03"); /* flush registers */
*(addr + RP_OFF) = jmp_addr + ADDR_ADJ_OFFSET;
- *(addr + SP_OFF) = (unsigned32)(_stack_high - CPU_FRAME_SIZE);
- *(addr + FP_OFF) = (unsigned32)(_stack_high);
+ *(addr + SP_OFF) = (uint32_t )(_stack_high - CPU_FRAME_SIZE);
+ *(addr + FP_OFF) = (uint32_t )(_stack_high);
#elif defined(__i386__)
@@ -540,7 +540,7 @@ void _CPU_Context_Initialize(
*/
{
- unsigned32 stack_ptr;
+ uint32_t stack_ptr;
stack_ptr = _stack_high - CPU_FRAME_SIZE;
@@ -551,11 +551,11 @@ void _CPU_Context_Initialize(
*(addr + ESP_OFF) = stack_ptr;
*(addr + RET_OFF) = jmp_addr;
- addr = (unsigned32 *) stack_ptr;
+ addr = (uint32_t *) stack_ptr;
addr[ 0 ] = jmp_addr;
- addr[ 1 ] = (unsigned32) stack_ptr;
- addr[ 2 ] = (unsigned32) stack_ptr;
+ addr[ 1 ] = (uint32_t ) stack_ptr;
+ addr[ 2 ] = (uint32_t ) stack_ptr;
}
#else
@@ -667,7 +667,7 @@ void _CPU_Restore_float_context(
* _CPU_ISR_Disable_support
*/
-unsigned32 _CPU_ISR_Disable_support(void)
+uint32_t _CPU_ISR_Disable_support(void)
{
int status;
sigset_t old_mask;
@@ -693,7 +693,7 @@ unsigned32 _CPU_ISR_Disable_support(void)
*/
void _CPU_ISR_Enable(
- unsigned32 level
+ uint32_t level
)
{
int status;
@@ -723,7 +723,7 @@ void _CPU_ISR_Enable(
void _CPU_ISR_Handler(int vector)
{
extern void _Thread_Dispatch(void);
- extern unsigned32 _Thread_Dispatch_disable_level;
+ extern uint32_t _Thread_Dispatch_disable_level;
extern boolean _Context_Switch_necessary;
if (_ISR_Nest_level++ == 0) {
@@ -833,7 +833,7 @@ void _CPU_Stray_signal(int sig_num)
* _CPU_Fatal_error
*/
-void _CPU_Fatal_error(unsigned32 error)
+void _CPU_Fatal_error(uint32_t error)
{
setitimer(ITIMER_REAL, 0, 0);
@@ -950,10 +950,10 @@ extern void fix_syscall_errno( void );
int _CPU_SHM_Semid;
void _CPU_SHM_Init(
- unsigned32 maximum_nodes,
+ uint32_t maximum_nodes,
boolean is_master_node,
void **shm_address,
- unsigned32 *shm_length
+ uint32_t *shm_length
)
{
int i;
diff --git a/cpukit/score/cpu/unix/rtems/score/cpu.h b/cpukit/score/cpu/unix/rtems/score/cpu.h
index 8b604fee80..0738d02bfc 100644
--- a/cpukit/score/cpu/unix/rtems/score/cpu.h
+++ b/cpukit/score/cpu/unix/rtems/score/cpu.h
@@ -466,7 +466,7 @@ extern "C" {
* This is really just the area for the following fields.
*
* jmp_buf regs;
- * unsigned32 isr_level;
+ * uint32_t isr_level;
*
* Doing it this way avoids conflicts between the native stuff and the
* RTEMS stuff.
@@ -506,10 +506,10 @@ typedef struct {
void (*postdriver_hook)( void );
void (*idle_task)( void );
boolean do_zero_of_workspace;
- unsigned32 idle_task_stack_size;
- unsigned32 interrupt_stack_size;
- unsigned32 extra_mpci_receive_server_stack;
- void * (*stack_allocate_hook)( unsigned32 );
+ uint32_t idle_task_stack_size;
+ uint32_t interrupt_stack_size;
+ uint32_t extra_mpci_receive_server_stack;
+ void * (*stack_allocate_hook)( uint32_t );
void (*stack_free_hook)( void* );
/* end of required fields */
} rtems_cpu_table;
@@ -682,7 +682,7 @@ void _CPU_Initialize_vectors(void);
* level is returned in _level.
*/
-extern unsigned32 _CPU_ISR_Disable_support(void);
+extern uint32_t _CPU_ISR_Disable_support(void);
#define _CPU_ISR_Disable( _level ) \
do { \
@@ -695,7 +695,7 @@ extern unsigned32 _CPU_ISR_Disable_support(void);
* _level is not modified.
*/
-void _CPU_ISR_Enable(unsigned32 level);
+void _CPU_ISR_Enable(uint32_t level);
/*
* This temporarily restores the interrupt to _level before immediately
@@ -706,7 +706,7 @@ void _CPU_ISR_Enable(unsigned32 level);
#define _CPU_ISR_Flash( _level ) \
do { \
- register unsigned32 _ignored = 0; \
+ register uint32_t _ignored = 0; \
_CPU_ISR_Enable( (_level) ); \
_CPU_ISR_Disable( _ignored ); \
} while ( 0 )
@@ -728,7 +728,7 @@ void _CPU_ISR_Enable(unsigned32 level);
else _CPU_ISR_Enable( 1 ); \
}
-unsigned32 _CPU_ISR_Get_level( void );
+uint32_t _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
@@ -789,9 +789,9 @@ unsigned32 _CPU_ISR_Get_level( void );
extern void _CPU_Context_Initialize(
Context_Control *_the_context,
- unsigned32 *_stack_base,
- unsigned32 _size,
- unsigned32 _new_level,
+ uint32_t *_stack_base,
+ uint32_t _size,
+ uint32_t _new_level,
void *_entry_point,
boolean _is_fp
);
@@ -910,7 +910,7 @@ void _CPU_Initialize(
*/
void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
@@ -922,7 +922,7 @@ void _CPU_ISR_install_raw_handler(
*/
void _CPU_ISR_install_vector(
- unsigned32 vector,
+ uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
);
@@ -995,11 +995,11 @@ void _CPU_Restore_float_context(
void _CPU_ISR_Set_signal_level(
- unsigned32 level
+ uint32_t level
);
void _CPU_Fatal_error(
- unsigned32 _error
+ uint32_t _error
);
/* The following routine swaps the endian format of an unsigned int.
@@ -1026,7 +1026,7 @@ static inline unsigned int CPU_swap_u32(
unsigned int value
)
{
- unsigned32 byte1, byte2, byte3, byte4, swapped;
+ uint32_t byte1, byte2, byte3, byte4, swapped;
byte4 = (value >> 24) & 0xff;
byte3 = (value >> 16) & 0xff;
@@ -1081,10 +1081,10 @@ void _CPU_Stop_clock( void );
#if defined(RTEMS_MULTIPROCESSING)
void _CPU_SHM_Init(
- unsigned32 maximum_nodes,
+ uint32_t maximum_nodes,
boolean is_master_node,
void **shm_address,
- unsigned32 *shm_length
+ uint32_t *shm_length
);
int _CPU_Get_pid( void );