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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-06-04 10:03:40 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-06-05 14:55:16 +0200 |
| commit | b938108b3d909a27aa8cd58fc410719be9220ad6 (patch) | |
| tree | 68ad42cf593802025128215562e51415081418a9 | |
| parent | bsps/arm: Simplify Cortex-A9 MPCore start (diff) | |
| download | rtems-b938108b3d909a27aa8cd58fc410719be9220ad6.tar.bz2 | |
bsps/arm: Cortex-A9 MPCore start
Add arm_a9mpcore_start_enable_smp_in_auxiliary_control().
| -rw-r--r-- | c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h index a3309ba005..155d33088e 100644 --- a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h +++ b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h @@ -125,6 +125,18 @@ arm_a9mpcore_start_on_secondary_processor(void) _SMP_Start_multitasking_on_secondary_processor(); } + +BSP_START_TEXT_SECTION static inline void +arm_a9mpcore_start_enable_smp_in_auxiliary_control(void) +{ + /* + * Enable cache coherency support and cache/MMU maintenance broadcasts for + * this processor. + */ + uint32_t actlr = arm_cp15_get_auxiliary_control(); + actlr |= ARM_CORTEX_A9_ACTL_SMP | ARM_CORTEX_A9_ACTL_FW; + arm_cp15_set_auxiliary_control(actlr); +} #endif BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_0(void) @@ -136,12 +148,7 @@ BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_0(void) arm_a9mpcore_start_scu_enable(scu); #ifdef RTEMS_SMP - /* Enable cache coherency support for this processor */ - { - uint32_t actlr = arm_cp15_get_auxiliary_control(); - actlr |= ARM_CORTEX_A9_ACTL_SMP | ARM_CORTEX_A9_ACTL_FW; - arm_cp15_set_auxiliary_control(actlr); - } + arm_a9mpcore_start_enable_smp_in_auxiliary_control(); #endif cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id(); |