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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-11-22 14:25:01 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-11-22 14:25:01 +0000 |
| commit | b7912a89de3e1f7315a55dae6a212cd3689c825f (patch) | |
| tree | d6779bf5cae57d801c967bac30eb77af5abd593d | |
| parent | Adding files missed by earlier merger of SH-2. (diff) | |
| download | rtems-b7912a89de3e1f7315a55dae6a212cd3689c825f.tar.bz2 | |
Changed name of W, X, and Y macros for fields in the Clock
Synthesizer Control Register to remove use of single letter names.
| -rw-r--r-- | c/src/exec/score/cpu/m68k/sim.h | 18 | ||||
| -rw-r--r-- | cpukit/score/cpu/m68k/rtems/m68k/sim.h | 18 | ||||
| -rw-r--r-- | cpukit/score/cpu/m68k/sim.h | 18 |
3 files changed, 27 insertions, 27 deletions
diff --git a/c/src/exec/score/cpu/m68k/sim.h b/c/src/exec/score/cpu/m68k/sim.h index d70f56d360..e1c637f9bd 100644 --- a/c/src/exec/score/cpu/m68k/sim.h +++ b/c/src/exec/score/cpu/m68k/sim.h @@ -108,15 +108,15 @@ #define SYNCR SIM_VOLATILE_USHORT_POINTER(0x04 + SIM_CRB) /* Clock Synthesizer Control Register */ -#define W 0x8000 /* Frequency Control (VCO) */ -#define X 0x4000 /* Frequency Control Bit (Prescale) */ -#define Y 0x3f00 /* Frequency Control Counter */ -#define EDIV 0x0080 /* ECLK Divide Rate */ -#define SLIMP 0x0010 /* Limp Mode Status */ -#define SLOCK 0x0008 /* Synthesizer Lock */ -#define RSTEN 0x0004 /* Reset Enable */ -#define STSIM 0x0002 /* Stop Mode SIM Clock */ -#define STEXT 0x0001 /* Stop Mode External Clock */ +#define VCO 0x8000 /* Frequency Control (VCO) */ +#define PRESCALE 0x4000 /* Frequency Control Bit (Prescale) */ +#define COUNTER 0x3f00 /* Frequency Control Counter */ +#define EDIV 0x0080 /* ECLK Divide Rate */ +#define SLIMP 0x0010 /* Limp Mode Status */ +#define SLOCK 0x0008 /* Synthesizer Lock */ +#define RSTEN 0x0004 /* Reset Enable */ +#define STSIM 0x0002 /* Stop Mode SIM Clock */ +#define STEXT 0x0001 /* Stop Mode External Clock */ diff --git a/cpukit/score/cpu/m68k/rtems/m68k/sim.h b/cpukit/score/cpu/m68k/rtems/m68k/sim.h index d70f56d360..e1c637f9bd 100644 --- a/cpukit/score/cpu/m68k/rtems/m68k/sim.h +++ b/cpukit/score/cpu/m68k/rtems/m68k/sim.h @@ -108,15 +108,15 @@ #define SYNCR SIM_VOLATILE_USHORT_POINTER(0x04 + SIM_CRB) /* Clock Synthesizer Control Register */ -#define W 0x8000 /* Frequency Control (VCO) */ -#define X 0x4000 /* Frequency Control Bit (Prescale) */ -#define Y 0x3f00 /* Frequency Control Counter */ -#define EDIV 0x0080 /* ECLK Divide Rate */ -#define SLIMP 0x0010 /* Limp Mode Status */ -#define SLOCK 0x0008 /* Synthesizer Lock */ -#define RSTEN 0x0004 /* Reset Enable */ -#define STSIM 0x0002 /* Stop Mode SIM Clock */ -#define STEXT 0x0001 /* Stop Mode External Clock */ +#define VCO 0x8000 /* Frequency Control (VCO) */ +#define PRESCALE 0x4000 /* Frequency Control Bit (Prescale) */ +#define COUNTER 0x3f00 /* Frequency Control Counter */ +#define EDIV 0x0080 /* ECLK Divide Rate */ +#define SLIMP 0x0010 /* Limp Mode Status */ +#define SLOCK 0x0008 /* Synthesizer Lock */ +#define RSTEN 0x0004 /* Reset Enable */ +#define STSIM 0x0002 /* Stop Mode SIM Clock */ +#define STEXT 0x0001 /* Stop Mode External Clock */ diff --git a/cpukit/score/cpu/m68k/sim.h b/cpukit/score/cpu/m68k/sim.h index d70f56d360..e1c637f9bd 100644 --- a/cpukit/score/cpu/m68k/sim.h +++ b/cpukit/score/cpu/m68k/sim.h @@ -108,15 +108,15 @@ #define SYNCR SIM_VOLATILE_USHORT_POINTER(0x04 + SIM_CRB) /* Clock Synthesizer Control Register */ -#define W 0x8000 /* Frequency Control (VCO) */ -#define X 0x4000 /* Frequency Control Bit (Prescale) */ -#define Y 0x3f00 /* Frequency Control Counter */ -#define EDIV 0x0080 /* ECLK Divide Rate */ -#define SLIMP 0x0010 /* Limp Mode Status */ -#define SLOCK 0x0008 /* Synthesizer Lock */ -#define RSTEN 0x0004 /* Reset Enable */ -#define STSIM 0x0002 /* Stop Mode SIM Clock */ -#define STEXT 0x0001 /* Stop Mode External Clock */ +#define VCO 0x8000 /* Frequency Control (VCO) */ +#define PRESCALE 0x4000 /* Frequency Control Bit (Prescale) */ +#define COUNTER 0x3f00 /* Frequency Control Counter */ +#define EDIV 0x0080 /* ECLK Divide Rate */ +#define SLIMP 0x0010 /* Limp Mode Status */ +#define SLOCK 0x0008 /* Synthesizer Lock */ +#define RSTEN 0x0004 /* Reset Enable */ +#define STSIM 0x0002 /* Stop Mode SIM Clock */ +#define STEXT 0x0001 /* Stop Mode External Clock */ |