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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-11-09 08:20:52 +0100 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-11-10 08:55:38 +0100 |
commit | a52fc42454ed0a682bb13319e5b63404be996f3b (patch) | |
tree | a3973a0db2e2e8aed0a724ffff93c6fb3693c192 | |
parent | bsps/riscv: Improve bsp_interrupt_vector_enable() (diff) | |
download | rtems-a52fc42454ed0a682bb13319e5b63404be996f3b.tar.bz2 |
bsps/riscv: Improve bsp_interrupt_vector_disable()
Add support for hart-specific software and timer interrupts.
-rw-r--r-- | bsps/riscv/riscv/irq/irq.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c index 3bce33ae13..238cb7f62a 100644 --- a/bsps/riscv/riscv/irq/irq.c +++ b/bsps/riscv/riscv/irq/irq.c @@ -500,8 +500,16 @@ rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) } rtems_interrupt_lock_release(&riscv_plic_lock, &lock_context); + return RTEMS_SUCCESSFUL; + } + + if (vector == RISCV_INTERRUPT_VECTOR_TIMER) { + clear_csr(mie, MIP_MTIP); + return RTEMS_SUCCESSFUL; } + _Assert(vector == RISCV_INTERRUPT_VECTOR_SOFTWARE); + clear_csr(mie, MIP_MSIP); return RTEMS_SUCCESSFUL; } |