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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2020-12-10 07:52:03 +0100 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2020-12-16 11:00:03 +0100 |
commit | a299c4feef70318c5098cb1d15557b37ac253d17 (patch) | |
tree | e5f0ba6deb4e843ab217f3903fb9585b372eeb86 | |
parent | bsps: Remove gicvx_interrupt_dispatch() (diff) | |
download | rtems-a299c4feef70318c5098cb1d15557b37ac253d17.tar.bz2 |
arm: Optimize arm_interrupt_disable()
Update #4202.
-rw-r--r-- | cpukit/score/cpu/arm/include/rtems/score/cpu.h | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/cpukit/score/cpu/arm/include/rtems/score/cpu.h b/cpukit/score/cpu/arm/include/rtems/score/cpu.h index 8a8e8cc617..e5b23e7100 100644 --- a/cpukit/score/cpu/arm/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/arm/include/rtems/score/cpu.h @@ -276,8 +276,6 @@ static inline uint32_t arm_interrupt_disable( void ) uint32_t level; #if defined(ARM_MULTILIB_ARCH_V4) - uint32_t arm_switch_reg; - /* * Disable only normal interrupts (IRQ). * @@ -292,6 +290,16 @@ static inline uint32_t arm_interrupt_disable( void ) * operating system support for a FIQ, she can trigger a software interrupt and * service the request in a two-step process. */ +#if __ARM_ARCH >= 7 + __asm__ volatile ( + "mrs %0, cpsr\n" + "cpsid i\n" + "isb" + : "=&r" (level) + ); +#else + uint32_t arm_switch_reg; + __asm__ volatile ( ARM_SWITCH_TO_ARM "mrs %[level], cpsr\n" @@ -300,6 +308,7 @@ static inline uint32_t arm_interrupt_disable( void ) ARM_SWITCH_BACK : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level) ); +#endif #elif defined(ARM_MULTILIB_ARCH_V7M) uint32_t basepri = 0x80; |