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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-01-03 16:35:08 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-01-03 16:35:08 +0000 |
| commit | 9fd4f5c5c2029548accfc814430fbbfd27e29e17 (patch) | |
| tree | af1fbea2ff8d29c3dd62c0afd10684fbc9cf4105 | |
| parent | 2001-01-03 Joel Sherrill <joel@OARcorp.com> (diff) | |
| download | rtems-9fd4f5c5c2029548accfc814430fbbfd27e29e17.tar.bz2 | |
2001-01-03 Joel Sherrill <joel@OARcorp.com>
* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
* cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
| -rw-r--r-- | c/src/exec/score/cpu/mips/ChangeLog | 5 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/mips/cpu_asm.S | 12 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/mips/rtems/score/cpu.h | 10 | ||||
| -rw-r--r-- | cpukit/score/cpu/mips/ChangeLog | 5 | ||||
| -rw-r--r-- | cpukit/score/cpu/mips/cpu_asm.S | 12 | ||||
| -rw-r--r-- | cpukit/score/cpu/mips/rtems/score/cpu.h | 10 |
6 files changed, 40 insertions, 14 deletions
diff --git a/c/src/exec/score/cpu/mips/ChangeLog b/c/src/exec/score/cpu/mips/ChangeLog index 86dfd0e121..aa76ef66c0 100644 --- a/c/src/exec/score/cpu/mips/ChangeLog +++ b/c/src/exec/score/cpu/mips/ChangeLog @@ -1,3 +1,8 @@ +2001-01-03 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). + * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN. + 2000-12-19 Joel Sherrill <joel@OARcorp.com> * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register. diff --git a/c/src/exec/score/cpu/mips/cpu_asm.S b/c/src/exec/score/cpu/mips/cpu_asm.S index 45d152de95..cc9e4ae4de 100644 --- a/c/src/exec/score/cpu/mips/cpu_asm.S +++ b/c/src/exec/score/cpu/mips/cpu_asm.S @@ -57,9 +57,9 @@ #endif #ifdef __GNUC__ -#define EXTERN(x,size) .extern x,size +#define ASM_EXTERN(x,size) .extern x,size #else -#define EXTERN(x,size) +#define ASM_EXTERN(x,size) #endif /* NOTE: these constants must match the Context_Control structure in cpu.h */ @@ -456,10 +456,10 @@ ENDFRAME(_CPU_Context_restore) #endif -EXTERN(_ISR_Nest_level, SZ_INT) -EXTERN(_Thread_Dispatch_disable_level,SZ_INT) -EXTERN(_Context_Switch_necessary,SZ_INT) -EXTERN(_ISR_Signals_to_thread_executing,SZ_INT) +ASM_EXTERN(_ISR_Nest_level, SZ_INT) +ASM_EXTERN(_Thread_Dispatch_disable_level,SZ_INT) +ASM_EXTERN(_Context_Switch_necessary,SZ_INT) +ASM_EXTERN(_ISR_Signals_to_thread_executing,SZ_INT) .extern _Thread_Dispatch .extern _ISR_Vector_table diff --git a/c/src/exec/score/cpu/mips/rtems/score/cpu.h b/c/src/exec/score/cpu/mips/rtems/score/cpu.h index 5ec59763a8..870d697f6c 100644 --- a/c/src/exec/score/cpu/mips/rtems/score/cpu.h +++ b/c/src/exec/score/cpu/mips/rtems/score/cpu.h @@ -582,7 +582,15 @@ extern unsigned int mips_interrupt_number_of_vectors; #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT -/* ISR handler macros */ +/* + * ISR handler macros + */ + +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + */ + +#define _CPU_Initialize_vectors() /* * Disable all interrupts for an RTEMS critical section. The previous diff --git a/cpukit/score/cpu/mips/ChangeLog b/cpukit/score/cpu/mips/ChangeLog index 86dfd0e121..aa76ef66c0 100644 --- a/cpukit/score/cpu/mips/ChangeLog +++ b/cpukit/score/cpu/mips/ChangeLog @@ -1,3 +1,8 @@ +2001-01-03 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). + * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN. + 2000-12-19 Joel Sherrill <joel@OARcorp.com> * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register. diff --git a/cpukit/score/cpu/mips/cpu_asm.S b/cpukit/score/cpu/mips/cpu_asm.S index 45d152de95..cc9e4ae4de 100644 --- a/cpukit/score/cpu/mips/cpu_asm.S +++ b/cpukit/score/cpu/mips/cpu_asm.S @@ -57,9 +57,9 @@ #endif #ifdef __GNUC__ -#define EXTERN(x,size) .extern x,size +#define ASM_EXTERN(x,size) .extern x,size #else -#define EXTERN(x,size) +#define ASM_EXTERN(x,size) #endif /* NOTE: these constants must match the Context_Control structure in cpu.h */ @@ -456,10 +456,10 @@ ENDFRAME(_CPU_Context_restore) #endif -EXTERN(_ISR_Nest_level, SZ_INT) -EXTERN(_Thread_Dispatch_disable_level,SZ_INT) -EXTERN(_Context_Switch_necessary,SZ_INT) -EXTERN(_ISR_Signals_to_thread_executing,SZ_INT) +ASM_EXTERN(_ISR_Nest_level, SZ_INT) +ASM_EXTERN(_Thread_Dispatch_disable_level,SZ_INT) +ASM_EXTERN(_Context_Switch_necessary,SZ_INT) +ASM_EXTERN(_ISR_Signals_to_thread_executing,SZ_INT) .extern _Thread_Dispatch .extern _ISR_Vector_table diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h index 5ec59763a8..870d697f6c 100644 --- a/cpukit/score/cpu/mips/rtems/score/cpu.h +++ b/cpukit/score/cpu/mips/rtems/score/cpu.h @@ -582,7 +582,15 @@ extern unsigned int mips_interrupt_number_of_vectors; #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT -/* ISR handler macros */ +/* + * ISR handler macros + */ + +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + */ + +#define _CPU_Initialize_vectors() /* * Disable all interrupts for an RTEMS critical section. The previous |