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authorJoel Sherrill <joel.sherrill@OARcorp.com>1999-02-02 21:56:15 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>1999-02-02 21:56:15 +0000
commit9e43ee55fb1b6f5d32b0fd6c11535c5800cdc1ea (patch)
tree8bab707a41f00dd13606b233733512c24c7f4996
parent13e11f69c1d20af4e202ffd101cfbf3c393602e5 (diff)
downloadrtems-9e43ee55fb1b6f5d32b0fd6c11535c5800cdc1ea.tar.bz2
New file.
-rw-r--r--c/src/exec/score/cpu/powerpc/ppccache.c61
1 files changed, 61 insertions, 0 deletions
diff --git a/c/src/exec/score/cpu/powerpc/ppccache.c b/c/src/exec/score/cpu/powerpc/ppccache.c
new file mode 100644
index 0000000000..ecfb4b96ca
--- /dev/null
+++ b/c/src/exec/score/cpu/powerpc/ppccache.c
@@ -0,0 +1,61 @@
+/*
+ * PowerPC Cache enable routines
+ *
+ * $Id$
+ */
+
+#include <rtems/system.h>
+
+#define PPC_Get_HID0( _value ) \
+ do { \
+ _value = 0; /* to avoid warnings */ \
+ asm volatile( \
+ "mfspr %0, 0x3f0;" /* get HID0 */ \
+ "isync" \
+ : "=r" (_value) \
+ : "0" (_value) \
+ ); \
+ } while (0)
+
+#define PPC_Set_HID0( _value ) \
+ do { \
+ asm volatile( \
+ "isync;" \
+ "mtspr 0x3f0, %0;" /* load HID0 */ \
+ "isync" \
+ : "=r" (_value) \
+ : "0" (_value) \
+ ); \
+ } while (0)
+
+
+void powerpc_instruction_cache_enable ()
+{
+ unsigned32 value;
+
+ /*
+ * Enable the instruction cache
+ */
+
+ PPC_Get_HID0( value );
+
+ value |= 0x00008000; /* Set ICE bit */
+
+ PPC_Set_HID0( value );
+}
+
+void powerpc_data_cache_enable ()
+{
+ unsigned32 value;
+
+ /*
+ * enable data cache
+ */
+
+ PPC_Get_HID0( value );
+
+ value |= 0x00004000; /* set DCE bit */
+
+ PPC_Set_HID0( value );
+}
+