bsps/sparc: Simplify memory initialization

Directly initialize the memory in the start sequence defined by start.S
instead of using a system initialization handler.  This avoids using the
global variable rdb_start which used a memory location which was shared
with _ERC32_MEC_Timer_Control_Mirror.  This change makes it possible to
use _Memory_Allocate() even before the system initialization is started.

Change license to BSD-2-Clause according to file history and
re-licensing agreement.

Update #3053.

2 files changed, 39 insertions, 34 deletions

diff --git a/bsps/sparc/shared/start/bspgetworkarea.c b/bsps/sparc/shared/start/bspgetworkarea.c
index 3fbeb824f2..6ceda38c07 100644
--- a/bsps/sparc/shared/start/bspgetworkarea.c
+++ b/bsps/sparc/shared/start/bspgetworkarea.c
@@ -1,44 +1,55 @@
+/**
+ * @file
+ *
+ * @ingroup RTEMSScoreMemory
+ *
+ * @brief This source file contains an implementation of _Memory_Get().
+ */
+
 /*
- *  This set of routines are the BSP specific initialization
- *  support routines.
+ * SPDX-License-Identifier: BSD-2-Clause
  *
- *  COPYRIGHT (c) 1989-2008.
- *  On-Line Applications Research Corporation (OAR).
+ * Copyright (C) 2019, 2021 embedded brains GmbH
  *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  */
 
 #include <bsp.h>
-#include <bsp/bootcard.h>
 
-#include <rtems/sysinit.h>
+#include <rtems/score/memory.h>
 
-/* Tells us where to put the workspace in case remote debugger is present.  */
-extern uintptr_t rdb_start;
+/* This function is called only by the start sequence defined in start.S */
+void _SPARC_Memory_initialize( void *end_of_usable_ram );
 
 static Memory_Area _Memory_Areas[ 1 ];
 
 static const Memory_Information _Memory_Information =
   MEMORY_INFORMATION_INITIALIZER( _Memory_Areas );
 
-static void bsp_memory_initialize( void )
+void _SPARC_Memory_initialize( void *end_of_usable_ram )
 {
-  void      *begin;
-  uintptr_t  size;
-
-  begin = &end;
-  size = rdb_start - (uintptr_t)begin;
-  _Memory_Initialize_by_size( &_Memory_Areas[ 0 ], begin, size );
+  _Memory_Initialize( &_Memory_Areas[ 0 ], &end, end_of_usable_ram );
 }
 
-RTEMS_SYSINIT_ITEM(
-  bsp_memory_initialize,
-  RTEMS_SYSINIT_MEMORY,
-  RTEMS_SYSINIT_ORDER_MIDDLE
-);
-
 const Memory_Information *_Memory_Get( void )
 {
   return &_Memory_Information;
diff --git a/bsps/sparc/shared/start/start.S b/bsps/sparc/shared/start/start.S
index c22509b038..13c3cffc00 100644
--- a/bsps/sparc/shared/start/start.S
+++ b/bsps/sparc/shared/start/start.S
@@ -178,16 +178,10 @@ SYM(trap_table):
    MEC timer control register mirror is so we can stop the timers
    from an external debugger. It is needed because the control
    register is write-only. Trap 0x7C cannot occure in ERC32...
-
-   We also use this location to store the last location of the
-   usable RAM in order not to overwrite the remote debugger with
-   the RTEMS work-space area.
-
 */
 
-	.global SYM(_ERC32_MEC_Timer_Control_Mirror), SYM(rdb_start), SYM(CLOCK_SPEED)
+	.global SYM(_ERC32_MEC_Timer_Control_Mirror), SYM(CLOCK_SPEED)
 
-SYM(rdb_start):
 SYM(_ERC32_MEC_Timer_Control_Mirror):
 
   BAD_TRAP; BAD_TRAP;                           ! 7C - 7D undefined
@@ -320,9 +314,6 @@ SYM(hard_reset):
 	st	%l7, [%l0]
 #endif
 
-	set	SYM(rdb_start), %g5	! End of RAM
-	st	%o0, [%g5]
-
         /* clear the bss */
 
         sethi %hi(__bss_start), %g2     ! g2 = start of bss
@@ -338,6 +329,9 @@ SYM(hard_reset):
         bleu,a .Lzerobss
         nop
 
+        call    SYM(_SPARC_Memory_initialize)
+         nop ! o0 = end of usable RAM provided by the boot loader
+
         call    SYM(boot_card)          ! does not return
          mov    %g0, %o0                ! command line