sparc64: Move libcpu content to cpukit

This patch is a part of the BSP source reorganization.

Update #3285.

12 files changed, 234 insertions, 356 deletions

diff --git a/c/src/lib/libbsp/sparc64/niagara/Makefile.am b/c/src/lib/libbsp/sparc64/niagara/Makefile.am
index 8ae6d0ce61..abe8e5a072 100644
--- a/c/src/lib/libbsp/sparc64/niagara/Makefile.am
+++ b/c/src/lib/libbsp/sparc64/niagara/Makefile.am
@@ -52,9 +52,5 @@ libbsp_a_SOURCES = $(startup_SOURCES) $(clock_SOURCES) $(console_SOURCES) \
 
 libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
 
-libbsp_a_LIBADD = \
-      ../../../libcpu/@RTEMS_CPU@/shared/shared-score.rel \
-      ../../../libcpu/@RTEMS_CPU@/shared/sparc64-syscall.rel 
-
 include $(top_srcdir)/../../../../automake/local.am
 include $(srcdir)/../../../../../../bsps/sparc64/niagara/headers.am
diff --git a/c/src/lib/libbsp/sparc64/niagara/make/custom/niagara.cfg b/c/src/lib/libbsp/sparc64/niagara/make/custom/niagara.cfg
index 117899318c..2fd8973bd6 100644
--- a/c/src/lib/libbsp/sparc64/niagara/make/custom/niagara.cfg
+++ b/c/src/lib/libbsp/sparc64/niagara/make/custom/niagara.cfg
@@ -4,10 +4,6 @@
 include $(RTEMS_ROOT)/make/custom/default.cfg
 
 RTEMS_CPU=sparc64
-RTEMS_CPU_MODEL=sun4v
-
-# This is the actual bsp directory used during the build process.
-RTEMS_BSP_FAMILY=niagara
 
 #  This contains the compiler options necessary to select the CPU model
 #  and (hopefully) optimize for it.
diff --git a/c/src/lib/libbsp/sparc64/usiii/Makefile.am b/c/src/lib/libbsp/sparc64/usiii/Makefile.am
index aedeac340f..6cbf9e7e99 100644
--- a/c/src/lib/libbsp/sparc64/usiii/Makefile.am
+++ b/c/src/lib/libbsp/sparc64/usiii/Makefile.am
@@ -65,9 +65,5 @@ libbsp_a_SOURCES = $(startup_SOURCES) $(mmu_SOURCES) $(clock_SOURCES) $(console_
 
 libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
 
-libbsp_a_LIBADD = \
-      ../../../libcpu/@RTEMS_CPU@/shared/shared-score.rel \
-      ../../../libcpu/@RTEMS_CPU@/shared/sparc64-syscall.rel 
-
 include $(top_srcdir)/../../../../automake/local.am
 include $(srcdir)/../../../../../../bsps/sparc64/usiii/headers.am
diff --git a/c/src/lib/libbsp/sparc64/usiii/make/custom/usiii.cfg b/c/src/lib/libbsp/sparc64/usiii/make/custom/usiii.cfg
index 740e5b6c34..b9fad21839 100644
--- a/c/src/lib/libbsp/sparc64/usiii/make/custom/usiii.cfg
+++ b/c/src/lib/libbsp/sparc64/usiii/make/custom/usiii.cfg
@@ -4,10 +4,6 @@
 include $(RTEMS_ROOT)/make/custom/default.cfg
 
 RTEMS_CPU=sparc64
-RTEMS_CPU_MODEL=sun4u
-
-# This is the actual bsp directory used during the build process.
-RTEMS_BSP_FAMILY=usiii
 
 #  This contains the compiler options necessary to select the CPU model
 #  and (hopefully) optimize for it.
diff --git a/c/src/lib/libcpu/sparc64/Makefile.am b/c/src/lib/libcpu/sparc64/Makefile.am
deleted file mode 100644
index d5883f5bd4..0000000000
--- a/c/src/lib/libcpu/sparc64/Makefile.am
+++ /dev/null
@@ -1,47 +0,0 @@
-ACLOCAL_AMFLAGS = -I ../../../aclocal
-
-include $(top_srcdir)/../../../automake/compile.am
-
-noinst_PROGRAMS =
-
-# NOTE: shared applies to targets meant to run with supervisor privilege,
-# i.e. sun4u or sun4v. Any targets (e.g. simulators) that cannot emulate 
-# supervisor privilege should use their own score and sparc64-syscall.
-# The other shared code is probably usable, but should be defined separately.
-# See the example at the end of Makefile.am.
-if shared
-
-noinst_PROGRAMS += shared/shared-score.rel
-shared_shared_score_rel_SOURCES = shared/score/cpu.c shared/score/interrupt.S
-shared_shared_score_rel_CPPFLAGS = $(AM_CPPFLAGS)
-shared_shared_score_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
-
-noinst_PROGRAMS += shared/sparc64-syscall.rel
-shared_sparc64_syscall_rel_SOURCES = shared/syscall/sparc64-syscall.S \
-  shared/syscall/sparc64-syscall.h
-shared_sparc64_syscall_rel_CPPFLAGS = $(AM_CPPFLAGS)
-shared_sparc64_syscall_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
-endif
-
-### This is an example of how to define a separate score implementation.
-## NOTE: Unlike other CPUs, we install into a subdirectory to avoid
-##       file name conflicts (See sh CPU for simexampleilar approach)
-#include_sparc64dir = $(includedir)/sparc64
-#include_rtems_scoredir = $(includedir)/rtems/score
-#
-#if simexample
-#include_sparc64_HEADERS =  
-#include_rtems_score_HEADERS = $(include_rtems_scoredir)/sparc64.h \
-#                              $(include_rtems_scoredir)/cpu.h \
-#                              $(include_rtems_scoredir)/types.h
-
-## simexample/score
-#noinst_PROGRAMS += simexample/score.rel
-#simexample_score_rel_SOURCES = 
-#simexample_score_rel_CPPFLAGS = $(AM_CPPFLAGS)
-#simexample_score_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
-#
-#endif
-### End of example.
-
-include $(top_srcdir)/../../../automake/local.am
diff --git a/c/src/lib/libcpu/sparc64/configure.ac b/c/src/lib/libcpu/sparc64/configure.ac
deleted file mode 100644
index 08607a53e7..0000000000
--- a/c/src/lib/libcpu/sparc64/configure.ac
+++ /dev/null
@@ -1,39 +0,0 @@
-## Process this file with autoconf to produce a configure script.
-
-AC_PREREQ([2.69])
-AC_INIT([rtems-c-src-lib-libcpu-sparc64],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
-AC_CONFIG_SRCDIR([shared])
-RTEMS_TOP([../../../../..],[../../..])
-RTEMS_SOURCE_TOP
-RTEMS_BUILD_TOP
-
-RTEMS_CANONICAL_TARGET_CPU
-
-AM_INIT_AUTOMAKE([no-define foreign subdir-objects 1.12.2])
-AM_MAINTAINER_MODE
-
-RTEMS_ENV_RTEMSBSP
-
-RTEMS_PROJECT_ROOT
-
-RTEMS_PROG_CC_FOR_TARGET
-AM_PROG_CC_C_O
-RTEMS_CANONICALIZE_TOOLS
-RTEMS_PROG_CCAS
-
-AM_CONDITIONAL(shared, test x"$RTEMS_CPU_MODEL" = x"sun4v" || \
-                       test x"$RTEMS_CPU_MODEL" = x"sun4u") 
-
-AM_CONDITIONAL([sun4u],[test x"$RTEMS_CPU_MODEL" = x"sun4u"])
-AM_CONDITIONAL([sun4v],[test x"$RTEMS_CPU_MODEL" = x"sun4v"])
-
-## How to add a conditional simexample for the Makefile.am, based on a
-## RTEMS_CPU_MODEL defined as simulator.
-#AM_CONDITIONAL([simexample],[test x"$RTEMS_CPU_MODEL" = x"simulator"])
-
-RTEMS_AMPOLISH3
-
-# Explicitly list all Makefiles here
-AC_CONFIG_FILES([Makefile])
-AC_OUTPUT
-
diff --git a/c/src/lib/libcpu/sparc64/shared/score/cpu.c b/c/src/lib/libcpu/sparc64/shared/score/cpu.c
deleted file mode 100644
index ca5ea9f09f..0000000000
--- a/c/src/lib/libcpu/sparc64/shared/score/cpu.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- *  SPARC-v9 Dependent Source
- */
-
-/*
- *  COPYRIGHT (c) 1989-2007. On-Line Applications Research Corporation (OAR).
- *
- *  This file is based on the SPARC cpu.c file. Modifications are made to 
- *  provide support for the SPARC-v9.
- *  COPYRIGHT (c) 2010. Gedare Bloom.
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#include <rtems/system.h>
-#include <rtems/asm.h>
-#include <rtems/score/isr.h>
-#include <rtems/rtems/cache.h>
-
-/*
- *  This initializes the set of opcodes placed in each trap
- *  table entry.  The routine which installs a handler is responsible
- *  for filling in the fields for the _handler address and the _vector
- *  trap type.
- *
- *  The constants following this structure are masks for the fields which
- *  must be filled in when the handler is installed.
- */
-
-/*  64-bit registers complicate this. Also, in sparc v9,
- *	each trap level gets its own set of global registers, but
- *	does not get its own dedicated register window. so we avoid
- *	using the local registers in the trap handler.
- */
-const CPU_Trap_table_entry _CPU_Trap_slot_template = {
-  0x89508000,	/* rdpr   %tstate, %g4       */
-  0x05000000,	/* sethi %hh(_handler), %g2  */
-  0x8410a000,	/* or     %g2, %hm(_handler), %g2 */
-  0x8528b020,	/* sllx   %g2, 32, %g2 */
-  0x07000000,	/* sethi  %hi(_handler), %g3 */
-  0x8610c002,	/* or     %g3, %g2, %g3 */
-  0x81c0e000, /* jmp   %g3 + %lo(_handler) */
-  0x84102000  /* mov   _vector, %g2        */
-};
-
-
-/*
- *  _CPU_ISR_Get_level
- *
- *  Input Parameters: NONE
- *
- *  Output Parameters:
- *    returns the current interrupt level (PIL field of the PSR)
- */
-uint32_t   _CPU_ISR_Get_level( void )
-{
-  uint32_t   level;
-
-  sparc64_get_interrupt_level( level );
-
-  return level;
-}
-
-/*
- *  _CPU_ISR_install_raw_handler
- *
- *  This routine installs the specified handler as a "raw" non-executive
- *  supported trap handler (a.k.a. interrupt service routine).
- *
- *  Input Parameters:
- *    vector      - trap table entry number plus synchronous
- *                    vs. asynchronous information
- *    new_handler - address of the handler to be installed
- *    old_handler - pointer to an address of the handler previously installed
- *
- *  Output Parameters: NONE
- *    *new_handler - address of the handler previously installed
- *
- *  NOTE:
- *
- *  On the SPARC v9, there are really only 512 vectors.  However, the executive
- *  has no easy, fast, reliable way to determine which traps are synchronous
- *  and which are asynchronous.  By default, traps return to the
- *  instruction which caused the interrupt.  So if you install a software
- *  trap handler as an executive interrupt handler (which is desirable since
- *  RTEMS takes care of window and register issues), then the executive needs
- *  to know that the return address is to the trap rather than the instruction
- *  following the trap.
- *
- *  So vectors 0 through 511 are treated as regular asynchronous traps which
- *  provide the "correct" return address.  Vectors 512 through 1023 are assumed
- *  by the executive to be synchronous and to require that the return be to the
- *  trapping instruction.
- *
- *  If you use this mechanism to install a trap handler which must reexecute
- *  the instruction which caused the trap, then it should be installed as
- *  a synchronous trap.  This will avoid the executive changing the return
- *  address.
- */
-void _CPU_ISR_install_raw_handler(
-  uint32_t    vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-)
-{
-  uint32_t               real_vector;
-  CPU_Trap_table_entry  *tba;
-  CPU_Trap_table_entry  *slot;
-  uint64_t               u64_tba;
-  uint64_t               u64_handler;
-
-  /*
-   *  Get the "real" trap number for this vector ignoring the synchronous
-   *  versus asynchronous indicator included with our vector numbers.
-   */
-
-  real_vector = SPARC_REAL_TRAP_NUMBER( vector );
-
-  /*
-   *  Get the current base address of the trap table and calculate a pointer
-   *  to the slot we are interested in.
-   */
-
-  sparc64_get_tba( u64_tba );
-
-/*  u32_tbr &= 0xfffff000; */
-  u64_tba &= 0xffffffffffff8000;  /* keep only trap base address */
-
-  tba = (CPU_Trap_table_entry *) u64_tba;
-
-  /* use array indexing to fill in lower bits -- require
-   * CPU_Trap_table_entry to be full-sized. */
-  slot = &tba[ real_vector ];
-
-  /*
-   *  Get the address of the old_handler from the trap table.
-   *
-   *  NOTE: The old_handler returned will be bogus if it does not follow
-   *        the RTEMS model.
-   */
-
-  /* shift amount to shift of hi bits (31:10) */
-#define HI_BITS_SHIFT  10
-
-  /* shift amount of hm bits (41:32) */
-#define HM_BITS_SHIFT  32
-
-  /* shift amount of hh bits (63:42) */
-#define HH_BITS_SHIFT  42
-
-  /* We're only interested in bits 0-9 of the immediate field*/
-#define IMM_MASK    0x000003FF
-
-  if ( slot->rdpr_tstate_g4 == _CPU_Trap_slot_template.rdpr_tstate_g4 ) {
-    u64_handler =
-      (((uint64_t)((slot->sethi_of_hh_handler_to_g2 << HI_BITS_SHIFT) |
-      (slot->or_g2_hm_handler_to_g2 & IMM_MASK))) << HM_BITS_SHIFT) |
-      ((slot->sethi_of_handler_to_g3 << HI_BITS_SHIFT) |
-      (slot->jmp_to_low_of_handler_plus_g3 & IMM_MASK));
-    *old_handler = (proc_ptr) u64_handler;
-  } else
-    *old_handler = 0;
-
-  /*
-   *  Copy the template to the slot and then fix it.
-   */
-
-  *slot = _CPU_Trap_slot_template;
-
-  u64_handler = (uint64_t) new_handler;
-
-  /* mask for extracting %hh */
-#define HH_BITS_MASK   0xFFFFFC0000000000
-
-  /* mask for extracting %hm */
-#define HM_BITS_MASK   0x000003FF00000000
-
-  /* mask for extracting %hi */
-#define HI_BITS_MASK   0x00000000FFFFFC00
-
-  /* mask for extracting %lo */
-#define LO_BITS_MASK   0x00000000000003FF
-
-
-  slot->mov_vector_g2 |= vector;
-  slot->sethi_of_hh_handler_to_g2 |=
-    (u64_handler & HH_BITS_MASK) >> HH_BITS_SHIFT;
-  slot->or_g2_hm_handler_to_g2 |=
-    (u64_handler & HM_BITS_MASK) >> HM_BITS_SHIFT;
-  slot->sethi_of_handler_to_g3 |=
-    (u64_handler & HI_BITS_MASK) >> HI_BITS_SHIFT;
-  slot->jmp_to_low_of_handler_plus_g3 |= (u64_handler & LO_BITS_MASK);
-
-  /* need to flush icache after this !!! */
-
-  /* need to flush icache in case old trap handler is in cache */
-  rtems_cache_invalidate_entire_instruction();
-
-}
-
-/*
- *  _CPU_ISR_install_vector
- *
- *  This kernel routine installs the RTEMS handler for the
- *  specified vector.
- *
- *  Input parameters:
- *    vector       - interrupt vector number
- *    new_handler  - replacement ISR for this vector number
- *    old_handler  - pointer to former ISR for this vector number
- *
- *  Output parameters:
- *    *old_handler - former ISR for this vector number
- */
-void _CPU_ISR_install_vector(
-  uint64_t    vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-)
-{
-   uint64_t   real_vector;
-   proc_ptr   ignored;
-
-  /*
-   *  Get the "real" trap number for this vector ignoring the synchronous
-   *  versus asynchronous indicator included with our vector numbers.
-   */
-   real_vector = SPARC_REAL_TRAP_NUMBER( vector );
-   /*
-    *  Return the previous ISR handler.
-    */
-
-   *old_handler = _ISR_Vector_table[ vector ];
-
-   /*
-    *  Install the wrapper so this ISR can be invoked properly.
-    */
-
-   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
-
-   /*
-    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
-    *  be used by the _ISR_Handler so the user gets control.
-    */
-
-    _ISR_Vector_table[ real_vector ] = new_handler;
-}
diff --git a/cpukit/score/cpu/sparc64/Makefile.am b/cpukit/score/cpu/sparc64/Makefile.am
index 2afd3edead..6cd23f0c95 100644
--- a/cpukit/score/cpu/sparc64/Makefile.am
+++ b/cpukit/score/cpu/sparc64/Makefile.am
@@ -1,13 +1,13 @@
 include $(top_srcdir)/automake/compile.am
 
-#include_rtems_sparc64dir = $(includedir)/rtems/sparc64
-#include_rtems_sparc64_HEADERS = 
-
 noinst_LIBRARIES = libscorecpu.a
-libscorecpu_a_SOURCES = context.S cpu.c
+libscorecpu_a_SOURCES =
+libscorecpu_a_SOURCES += context.S
+libscorecpu_a_SOURCES += cpu.c
+libscorecpu_a_SOURCES += interrupt.S
 libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c
 libscorecpu_a_SOURCES += sparc64-exception-frame-print.c
-libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
+libscorecpu_a_SOURCES += sparc64-syscall.S
 
 include $(top_srcdir)/automake/local.am
 include $(srcdir)/headers.am
diff --git a/cpukit/score/cpu/sparc64/cpu.c b/cpukit/score/cpu/sparc64/cpu.c
index 93a4573c72..7eb80988b1 100644
--- a/cpukit/score/cpu/sparc64/cpu.c
+++ b/cpukit/score/cpu/sparc64/cpu.c
@@ -110,3 +110,232 @@ void _CPU_Context_Initialize(
     the_context->g7 = (uintptr_t) tcb;
   }
 }
+
+/*
+ *  This initializes the set of opcodes placed in each trap
+ *  table entry.  The routine which installs a handler is responsible
+ *  for filling in the fields for the _handler address and the _vector
+ *  trap type.
+ *
+ *  The constants following this structure are masks for the fields which
+ *  must be filled in when the handler is installed.
+ */
+
+/*  64-bit registers complicate this. Also, in sparc v9,
+ *	each trap level gets its own set of global registers, but
+ *	does not get its own dedicated register window. so we avoid
+ *	using the local registers in the trap handler.
+ */
+const CPU_Trap_table_entry _CPU_Trap_slot_template = {
+  0x89508000,	/* rdpr   %tstate, %g4       */
+  0x05000000,	/* sethi %hh(_handler), %g2  */
+  0x8410a000,	/* or     %g2, %hm(_handler), %g2 */
+  0x8528b020,	/* sllx   %g2, 32, %g2 */
+  0x07000000,	/* sethi  %hi(_handler), %g3 */
+  0x8610c002,	/* or     %g3, %g2, %g3 */
+  0x81c0e000, /* jmp   %g3 + %lo(_handler) */
+  0x84102000  /* mov   _vector, %g2        */
+};
+
+
+/*
+ *  _CPU_ISR_Get_level
+ *
+ *  Input Parameters: NONE
+ *
+ *  Output Parameters:
+ *    returns the current interrupt level (PIL field of the PSR)
+ */
+uint32_t   _CPU_ISR_Get_level( void )
+{
+  uint32_t   level;
+
+  sparc64_get_interrupt_level( level );
+
+  return level;
+}
+
+/*
+ *  _CPU_ISR_install_raw_handler
+ *
+ *  This routine installs the specified handler as a "raw" non-executive
+ *  supported trap handler (a.k.a. interrupt service routine).
+ *
+ *  Input Parameters:
+ *    vector      - trap table entry number plus synchronous
+ *                    vs. asynchronous information
+ *    new_handler - address of the handler to be installed
+ *    old_handler - pointer to an address of the handler previously installed
+ *
+ *  Output Parameters: NONE
+ *    *new_handler - address of the handler previously installed
+ *
+ *  NOTE:
+ *
+ *  On the SPARC v9, there are really only 512 vectors.  However, the executive
+ *  has no easy, fast, reliable way to determine which traps are synchronous
+ *  and which are asynchronous.  By default, traps return to the
+ *  instruction which caused the interrupt.  So if you install a software
+ *  trap handler as an executive interrupt handler (which is desirable since
+ *  RTEMS takes care of window and register issues), then the executive needs
+ *  to know that the return address is to the trap rather than the instruction
+ *  following the trap.
+ *
+ *  So vectors 0 through 511 are treated as regular asynchronous traps which
+ *  provide the "correct" return address.  Vectors 512 through 1023 are assumed
+ *  by the executive to be synchronous and to require that the return be to the
+ *  trapping instruction.
+ *
+ *  If you use this mechanism to install a trap handler which must reexecute
+ *  the instruction which caused the trap, then it should be installed as
+ *  a synchronous trap.  This will avoid the executive changing the return
+ *  address.
+ */
+void _CPU_ISR_install_raw_handler(
+  uint32_t    vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+  uint32_t               real_vector;
+  CPU_Trap_table_entry  *tba;
+  CPU_Trap_table_entry  *slot;
+  uint64_t               u64_tba;
+  uint64_t               u64_handler;
+
+  /*
+   *  Get the "real" trap number for this vector ignoring the synchronous
+   *  versus asynchronous indicator included with our vector numbers.
+   */
+
+  real_vector = SPARC_REAL_TRAP_NUMBER( vector );
+
+  /*
+   *  Get the current base address of the trap table and calculate a pointer
+   *  to the slot we are interested in.
+   */
+
+  sparc64_get_tba( u64_tba );
+
+/*  u32_tbr &= 0xfffff000; */
+  u64_tba &= 0xffffffffffff8000;  /* keep only trap base address */
+
+  tba = (CPU_Trap_table_entry *) u64_tba;
+
+  /* use array indexing to fill in lower bits -- require
+   * CPU_Trap_table_entry to be full-sized. */
+  slot = &tba[ real_vector ];
+
+  /*
+   *  Get the address of the old_handler from the trap table.
+   *
+   *  NOTE: The old_handler returned will be bogus if it does not follow
+   *        the RTEMS model.
+   */
+
+  /* shift amount to shift of hi bits (31:10) */
+#define HI_BITS_SHIFT  10
+
+  /* shift amount of hm bits (41:32) */
+#define HM_BITS_SHIFT  32
+
+  /* shift amount of hh bits (63:42) */
+#define HH_BITS_SHIFT  42
+
+  /* We're only interested in bits 0-9 of the immediate field*/
+#define IMM_MASK    0x000003FF
+
+  if ( slot->rdpr_tstate_g4 == _CPU_Trap_slot_template.rdpr_tstate_g4 ) {
+    u64_handler =
+      (((uint64_t)((slot->sethi_of_hh_handler_to_g2 << HI_BITS_SHIFT) |
+      (slot->or_g2_hm_handler_to_g2 & IMM_MASK))) << HM_BITS_SHIFT) |
+      ((slot->sethi_of_handler_to_g3 << HI_BITS_SHIFT) |
+      (slot->jmp_to_low_of_handler_plus_g3 & IMM_MASK));
+    *old_handler = (proc_ptr) u64_handler;
+  } else
+    *old_handler = 0;
+
+  /*
+   *  Copy the template to the slot and then fix it.
+   */
+
+  *slot = _CPU_Trap_slot_template;
+
+  u64_handler = (uint64_t) new_handler;
+
+  /* mask for extracting %hh */
+#define HH_BITS_MASK   0xFFFFFC0000000000
+
+  /* mask for extracting %hm */
+#define HM_BITS_MASK   0x000003FF00000000
+
+  /* mask for extracting %hi */
+#define HI_BITS_MASK   0x00000000FFFFFC00
+
+  /* mask for extracting %lo */
+#define LO_BITS_MASK   0x00000000000003FF
+
+
+  slot->mov_vector_g2 |= vector;
+  slot->sethi_of_hh_handler_to_g2 |=
+    (u64_handler & HH_BITS_MASK) >> HH_BITS_SHIFT;
+  slot->or_g2_hm_handler_to_g2 |=
+    (u64_handler & HM_BITS_MASK) >> HM_BITS_SHIFT;
+  slot->sethi_of_handler_to_g3 |=
+    (u64_handler & HI_BITS_MASK) >> HI_BITS_SHIFT;
+  slot->jmp_to_low_of_handler_plus_g3 |= (u64_handler & LO_BITS_MASK);
+
+  /* need to flush icache after this !!! */
+
+  /* need to flush icache in case old trap handler is in cache */
+  rtems_cache_invalidate_entire_instruction();
+
+}
+
+/*
+ *  _CPU_ISR_install_vector
+ *
+ *  This kernel routine installs the RTEMS handler for the
+ *  specified vector.
+ *
+ *  Input parameters:
+ *    vector       - interrupt vector number
+ *    new_handler  - replacement ISR for this vector number
+ *    old_handler  - pointer to former ISR for this vector number
+ *
+ *  Output parameters:
+ *    *old_handler - former ISR for this vector number
+ */
+void _CPU_ISR_install_vector(
+  uint64_t    vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+   uint64_t   real_vector;
+   proc_ptr   ignored;
+
+  /*
+   *  Get the "real" trap number for this vector ignoring the synchronous
+   *  versus asynchronous indicator included with our vector numbers.
+   */
+   real_vector = SPARC_REAL_TRAP_NUMBER( vector );
+   /*
+    *  Return the previous ISR handler.
+    */
+
+   *old_handler = _ISR_Vector_table[ vector ];
+
+   /*
+    *  Install the wrapper so this ISR can be invoked properly.
+    */
+
+   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
+
+   /*
+    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
+    *  be used by the _ISR_Handler so the user gets control.
+    */
+
+    _ISR_Vector_table[ real_vector ] = new_handler;
+}
diff --git a/c/src/lib/libcpu/sparc64/shared/score/interrupt.S b/cpukit/score/cpu/sparc64/interrupt.S
index 6f8eb373f0..6f8eb373f0 100644
--- a/c/src/lib/libcpu/sparc64/shared/score/interrupt.S
+++ b/cpukit/score/cpu/sparc64/interrupt.S
diff --git a/c/src/lib/libcpu/sparc64/shared/syscall/sparc64-syscall.S b/cpukit/score/cpu/sparc64/sparc64-syscall.S
index ffd6e8538d..ffd6e8538d 100644
--- a/c/src/lib/libcpu/sparc64/shared/syscall/sparc64-syscall.S
+++ b/cpukit/score/cpu/sparc64/sparc64-syscall.S
diff --git a/c/src/lib/libcpu/sparc64/shared/syscall/sparc64-syscall.h b/cpukit/score/cpu/sparc64/sparc64-syscall.h
index 9af3560267..9af3560267 100644
--- a/c/src/lib/libcpu/sparc64/shared/syscall/sparc64-syscall.h
+++ b/cpukit/score/cpu/sparc64/sparc64-syscall.h