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| author | Kevin Kirspel <Kevin-Kirspel@idexx.com> | 2016-08-19 07:38:07 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2016-08-19 07:40:45 +0200 |
| commit | 36fad91f00360db3a45e3046ae7b62ae13fac9fd (patch) | |
| tree | 4efcdf0a5ed8b358f44a6140f400bcf4550fcd6a | |
| parent | bsp/atsam: Add timeout to QSPI send command (diff) | |
| download | rtems-36fad91f00360db3a45e3046ae7b62ae13fac9fd.tar.bz2 | |
arm: Add VFP context validate support for ARMv5
| -rw-r--r-- | cpukit/score/cpu/arm/arm-context-validate.S | 9 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/arm-context-volatile-clobber.S | 7 |
2 files changed, 11 insertions, 5 deletions
diff --git a/cpukit/score/cpu/arm/arm-context-validate.S b/cpukit/score/cpu/arm/arm-context-validate.S index fdfb6c156b..5bb2e25f6d 100644 --- a/cpukit/score/cpu/arm/arm-context-validate.S +++ b/cpukit/score/cpu/arm/arm-context-validate.S @@ -46,7 +46,11 @@ .section .text +#ifdef __thumb__ FUNCTION_THUMB_ENTRY(_CPU_Context_validate) +#else +FUNCTION_ENTRY(_CPU_Context_validate) +#endif /* Save */ @@ -99,11 +103,10 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_validate) #ifdef ARM_MULTILIB_VFP /* R3 contains the FPSCR */ vmrs r3, FPSCR - movs r4, #0x001f #ifdef ARM_MULTILIB_ARCH_V7M - movt r4, #0xf000 + ldr r4, =0xf000001f #else - movt r4, #0xf800 + ldr r4, =0xf800001f #endif bic r3, r3, r4 and r4, r4, r0 diff --git a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S index 7970b8e690..b3c9d7739b 100644 --- a/cpukit/score/cpu/arm/arm-context-volatile-clobber.S +++ b/cpukit/score/cpu/arm/arm-context-volatile-clobber.S @@ -20,7 +20,11 @@ .section .text +#ifdef __thumb__ FUNCTION_THUMB_ENTRY(_CPU_Context_volatile_clobber) +#else +FUNCTION_ENTRY(_CPU_Context_volatile_clobber) +#endif .macro clobber_register reg sub r0, r0, #1 @@ -29,8 +33,7 @@ FUNCTION_THUMB_ENTRY(_CPU_Context_volatile_clobber) #ifdef ARM_MULTILIB_VFP vmrs r1, FPSCR - movs r2, #0x001f - movt r2, #0xf800 + ldr r2, =0xf800001f bic r1, r1, r2 and r2, r2, r0 orr r1, r1, r2 |