bsps/aarch64: Use MMU pages appropriately

There were two bugs with MMU page use that were partially hiding each
other. The linker script page table section was 4x the size it needed to
be and the page table allocation routine was allocating pages PTRSIZE
times larger than it needed to. On ILP32, this resulted in incorrect but
functional allocation. On LP64, this resulted in allocation failures
earlier than expected.

5 files changed, 14 insertions, 14 deletions

diff --git a/bsps/aarch64/include/bsp/aarch64-mmu.h b/bsps/aarch64/include/bsp/aarch64-mmu.h
index 6e589cd6cd..bca7e0ce8d 100644
--- a/bsps/aarch64/include/bsp/aarch64-mmu.h
+++ b/bsps/aarch64/include/bsp/aarch64-mmu.h
@@ -145,8 +145,8 @@ BSP_START_TEXT_SECTION static inline rtems_status_code
 aarch64_mmu_page_table_alloc( uint64_t **page_table )
 {
   /* First page table is already in use as TTB0 */
-  static uintptr_t *current_page_table =
-    (uintptr_t *) bsp_translation_table_base;
+  static uintptr_t current_page_table =
+    (uintptr_t) bsp_translation_table_base;
 
   current_page_table += MMU_PAGE_SIZE;
   *page_table = (uint64_t *) current_page_table;
diff --git a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
index 3030fd0ae9..2d7a922495 100644
--- a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
+++ b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml
@@ -29,9 +29,9 @@ content: |
    */
 
   MEMORY {
-    RAM       : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
-    NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
-    RAM_MMU   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
+    RAM       : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
+    NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
+    RAM_MMU   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
   }
 
   REGION_ALIAS ("REGION_START",          RAM);
diff --git a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
index bd5d1f791b..76c0220f0e 100644
--- a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
+++ b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml
@@ -29,9 +29,9 @@ content: |
    */
 
   MEMORY {
-    RAM       : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
-    NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
-    RAM_MMU   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
+    RAM       : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
+    NOCACHE   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}
+    RAM_MMU   : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
   }
 
   REGION_ALIAS ("REGION_START",          RAM);
diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_ilp32.yml b/spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_ilp32.yml
index b530969de7..568e663c49 100644
--- a/spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_ilp32.yml
+++ b/spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_ilp32.yml
@@ -30,9 +30,9 @@ content: |
    */
 
   MEMORY {
-    RAM       : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - ${BSP_XILINX_ZYNQMP_LOAD_OFFSET} - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
-    NOCACHE   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}
-    RAM_MMU   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
+    RAM       : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - ${BSP_XILINX_ZYNQMP_LOAD_OFFSET} - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
+    NOCACHE   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}
+    RAM_MMU   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
   }
 
   REGION_ALIAS ("REGION_START",          RAM);
diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_lp64.yml b/spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_lp64.yml
index d9696be5d4..4a26c59944 100644
--- a/spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_lp64.yml
+++ b/spec/build/bsps/aarch64/xilinx-zynqmp/linkcmds_lp64.yml
@@ -30,9 +30,9 @@ content: |
    */
 
   MEMORY {
-    RAM       : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - ${BSP_XILINX_ZYNQMP_LOAD_OFFSET} - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
-    NOCACHE   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}
-    RAM_MMU   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
+    RAM       : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - ${BSP_XILINX_ZYNQMP_LOAD_OFFSET} - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES})
+    NOCACHE   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_ZYNQMP_NOCACHE_LENGTH}
+    RAM_MMU   : ORIGIN = ${BSP_XILINX_ZYNQMP_RAM_BASE} + ${BSP_XILINX_ZYNQMP_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}
   }
 
   REGION_ALIAS ("REGION_START",          RAM);