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authorJay Monkman <jtm@smoothsmoothie.com>2004-07-15 06:12:05 +0000
committerJay Monkman <jtm@smoothsmoothie.com>2004-07-15 06:12:05 +0000
commit1a3d1f3e80f14a156a432a835983ce46c039e24a (patch)
tree625ed5fb9bca70c6f7316691b64d332d6ec85e9e
parent2004-07-15 Jay Monkman (diff)
downloadrtems-1a3d1f3e80f14a156a432a835983ce46c039e24a.tar.bz2
2004-07-15 Jay Monkman
* ChangeLog, Makefile.am, README, bsp_specs, configure.ac, times, console/uart.c, include/bsp.h, include/tm27.h, network/lan91c11x.c, network/lan91c11x.h, network/network.c, start/start.S, startup/bspstart.c, startup/exit.c, startup/linkcmds, startup/memmap.c: New files.
-rw-r--r--c/src/lib/libbsp/arm/csb336/ChangeLog8
-rw-r--r--c/src/lib/libbsp/arm/csb336/Makefile.am149
-rw-r--r--c/src/lib/libbsp/arm/csb336/README7
-rw-r--r--c/src/lib/libbsp/arm/csb336/bsp_specs23
-rw-r--r--c/src/lib/libbsp/arm/csb336/configure.ac24
-rw-r--r--c/src/lib/libbsp/arm/csb336/console/uart.c262
-rw-r--r--c/src/lib/libbsp/arm/csb336/include/bsp.h61
-rw-r--r--c/src/lib/libbsp/arm/csb336/include/tm27.h32
-rw-r--r--c/src/lib/libbsp/arm/csb336/network/lan91c11x.c267
-rw-r--r--c/src/lib/libbsp/arm/csb336/network/lan91c11x.h216
-rw-r--r--c/src/lib/libbsp/arm/csb336/network/network.c724
-rw-r--r--c/src/lib/libbsp/arm/csb336/start/start.S147
-rw-r--r--c/src/lib/libbsp/arm/csb336/startup/bspstart.c233
-rw-r--r--c/src/lib/libbsp/arm/csb336/startup/exit.c36
-rw-r--r--c/src/lib/libbsp/arm/csb336/startup/linkcmds240
-rw-r--r--c/src/lib/libbsp/arm/csb336/startup/memmap.c34
-rw-r--r--c/src/lib/libbsp/arm/csb336/times189
17 files changed, 2652 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/csb336/ChangeLog b/c/src/lib/libbsp/arm/csb336/ChangeLog
new file mode 100644
index 0000000000..167be43dac
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/ChangeLog
@@ -0,0 +1,8 @@
+2004-07-15 Jay Monkman
+
+ * ChangeLog, Makefile.am, README, bsp_specs, configure.ac, times,
+ console/uart.c, include/bsp.h, include/tm27.h, network/lan91c11x.c,
+ network/lan91c11x.h, network/network.c, start/start.S,
+ startup/bspstart.c, startup/exit.c, startup/linkcmds,
+ startup/memmap.c: New files.
+
diff --git a/c/src/lib/libbsp/arm/csb336/Makefile.am b/c/src/lib/libbsp/arm/csb336/Makefile.am
new file mode 100644
index 0000000000..86746fee1f
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/Makefile.am
@@ -0,0 +1,149 @@
+##
+## $Id$
+##
+
+ACLOCAL_AMFLAGS = -I ../../../../aclocal
+
+include $(top_srcdir)/../../../../automake/compile.am
+include $(top_srcdir)/../../bsp.am
+
+dist_project_lib_DATA = bsp_specs
+
+include_HEADERS = include/bsp.h
+include_HEADERS += include/tm27.h
+nodist_include_HEADERS = include/bspopts.h
+
+EXTRA_PROGRAMS =
+CLEANFILES =
+noinst_DATA =
+
+nodist_include_HEADERS += ../../shared/include/coverhd.h
+
+EXTRA_DIST = start/start.S
+start$(LIB_VARIANT).$(OBJEXT): start/start.S
+ $(CPPASCOMPILE) -DASM -o $@ -c $<
+project_lib_DATA = start$(LIB_VARIANT).$(OBJEXT)
+
+dist_project_lib_DATA += startup/linkcmds
+
+EXTRA_PROGRAMS += startup.rel
+CLEANFILES += startup.rel
+startup_rel_SOURCES = ../../shared/bsplibc.c ../../shared/bsppost.c \
+ startup/bspstart.c startup/exit.c \
+ startup/memmap.c \
+ ../../shared/bootcard.c \
+ ../../shared/main.c ../../shared/sbrk.c \
+ ../../shared/gnatinstallhandler.c
+startup_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_OPTIMIZE_V)
+startup_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+EXTRA_PROGRAMS += startup_g.rel
+CLEANFILES += startup_g.rel
+startup_g_rel_SOURCES = $(startup_rel_SOURCES)
+startup_g_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_DEBUG_V)
+startup_g_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+noinst_DATA += startup$(LIB_VARIANT).rel
+
+EXTRA_PROGRAMS += console.rel
+CLEANFILES += console.rel
+console_rel_SOURCES = console/uart.c ../../shared/console.c
+console_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_OPTIMIZE_V)
+console_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+EXTRA_PROGRAMS += console_g.rel
+CLEANFILES += console_g.rel
+console_g_rel_SOURCES = $(console_rel_SOURCES)
+console_g_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_DEBUG_V)
+console_g_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+noinst_DATA += console$(LIB_VARIANT).rel
+
+if HAS_NETWORKING
+network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
+EXTRA_PROGRAMS += network.rel
+CLEANFILES += network.rel
+network_rel_SOURCES = network/network.c network/lan91c11x.c
+network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_OPTIMIZE_V) \
+ $(network_CPPFLAGS)
+network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+EXTRA_PROGRAMS += network_g.rel
+CLEANFILES += network_g.rel
+network_g_rel_SOURCES = $(network_rel_SOURCES)
+network_g_rel_CPPFLAGS = $(AM_CPPFLAGS) $(CFLAGS_DEBUG_V) \
+ $(network_CPPFLAGS)
+network_g_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
+
+noinst_DATA += network$(LIB_VARIANT).rel
+endif
+
+EXTRA_LIBRARIES = libbsp.a
+CLEANFILES += libbsp.a
+libbsp_a_SOURCES =
+libbsp_a_LIBADD = startup$(LIB_VARIANT).rel console$(LIB_VARIANT).rel
+if HAS_NETWORKING
+libbsp_a_LIBADD += network$(LIB_VARIANT).rel
+endif
+libbsp_a_LIBADD += \
+ ../../../libcpu/@RTEMS_CPU@/shared/arm920$(LIB_VARIANT).rel \
+ ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/clock$(LIB_VARIANT).rel \
+ ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/timer$(LIB_VARIANT).rel \
+ ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/irq$(LIB_VARIANT).rel
+
+EXTRA_LIBRARIES += libbsp_g.a
+CLEANFILES += libbsp_g.a
+libbsp_g_a_SOURCES = $(libbsp_a_SOURCES)
+libbsp_g_a_LIBADD = $(libbsp_a_LIBADD)
+
+noinst_DATA += libbsp$(LIB_VARIANT).a
+
+all-local: $(PREINSTALL_FILES) $(TMPINSTALL_FILES)
+
+PREINSTALL_DIRS =
+PREINSTALL_FILES =
+TMPINSTALL_FILES =
+
+$(PROJECT_INCLUDE)/$(dirstamp):
+ @$(mkdir_p) $(PROJECT_INCLUDE)
+ @: > $(PROJECT_INCLUDE)/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
+
+$(PROJECT_LIB)/$(dirstamp):
+ @$(mkdir_p) $(PROJECT_LIB)
+ @: > $(PROJECT_LIB)/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
+
+$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
+PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
+
+$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
+
+$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
+
+$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
+
+$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
+
+$(PROJECT_LIB)/start$(LIB_VARIANT).$(OBJEXT): start$(LIB_VARIANT).$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_LIB)/start$(LIB_VARIANT).$(OBJEXT)
+TMPINSTALL_FILES += $(PROJECT_LIB)/start$(LIB_VARIANT).$(OBJEXT)
+
+$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
+PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
+
+CLEANFILES += $(PREINSTALL_FILES)
+DISTCLEANFILES = $(PREINSTALL_DIRS)
+CLEANFILES += $(TMPINSTALL_FILES)
+
+include $(top_srcdir)/../../../../automake/local.am
diff --git a/c/src/lib/libbsp/arm/csb336/README b/c/src/lib/libbsp/arm/csb336/README
new file mode 100644
index 0000000000..e807c0d372
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/README
@@ -0,0 +1,7 @@
+#
+# $Id$
+#
+
+This is the BSP for Cogent Computer System's CSB336, a single board
+computer using the Motorola MC9328MXL CPU.
+
diff --git a/c/src/lib/libbsp/arm/csb336/bsp_specs b/c/src/lib/libbsp/arm/csb336/bsp_specs
new file mode 100644
index 0000000000..2309f0e53b
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/bsp_specs
@@ -0,0 +1,23 @@
+%rename cpp old_cpp
+%rename lib old_lib
+%rename endfile old_endfile
+%rename startfile old_startfile
+%rename link old_link
+
+*cpp:
+%(old_cpp) %{qrtems: -D__embedded__ -DUSE_ENHANCED_INTR_API} -Asystem(embedded)
+
+*lib:
+%{!qrtems: %(old_lib)} %{qrtems: --start-group \
+%{!qrtems_debug: -lrtemsbsp -lrtemscpu} %{qrtems_debug: -lrtemsbsp_g -lrtemscpu_g} \
+-lc -lgcc --end-group \
+%{!qnolinkcmds: -T linkcmds%s}}
+
+*startfile:
+%{!qrtems: %(old_startfile)} %{qrtems: \
+%{!qrtems_debug: start.o%s crtbegin.o%s} \
+%{qrtems_debug: start_g.o%s crtbegin.o%s}}
+
+*link:
+%{!qrtems: %(old_link)} %{qrtems: -Qy -dp -Bstatic -N -e _start}
+
diff --git a/c/src/lib/libbsp/arm/csb336/configure.ac b/c/src/lib/libbsp/arm/csb336/configure.ac
new file mode 100644
index 0000000000..8a9c0a35e8
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/configure.ac
@@ -0,0 +1,24 @@
+## Process this file with autoconf to produce a configure script.
+##
+## configure.ac,v 1.5 2003/03/11 09:39:07 ralf Exp
+
+AC_PREREQ(2.57)
+AC_INIT([rtems-c-src-lib-libbsp-arm-csb336],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com])
+AC_CONFIG_SRCDIR([bsp_specs])
+RTEMS_TOP(../../../../../..)
+
+RTEMS_CANONICAL_TARGET_CPU
+AM_INIT_AUTOMAKE([no-define foreign 1.8])
+RTEMS_BSP_CONFIGURE
+
+RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm])
+RTEMS_CANONICALIZE_TOOLS
+RTEMS_PROG_CCAS
+
+RTEMS_CHECK_NETWORKING
+AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
+
+# Explicitly list all Makefiles here
+AC_CONFIG_FILES([Makefile])
+AC_OUTPUT
+
diff --git a/c/src/lib/libbsp/arm/csb336/console/uart.c b/c/src/lib/libbsp/arm/csb336/console/uart.c
new file mode 100644
index 0000000000..c3df1382be
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/console/uart.c
@@ -0,0 +1,262 @@
+/*
+ * console driver for MC9328XML UARTs
+ *
+ * This driver uses the shared console driver in
+ * ...../libbsp/shared/console.c
+ *
+ * If you want the driver to be interrupt driven, you
+ * need to write the ISR, and in the ISR insert the
+ * chars into termios's queue.
+ *
+ * Copyright (c) 2004 Cogent Computer Systems
+ * Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ *
+ * $Id$
+*/
+#include <bsp.h> /* Must be before libio.h */
+#include <rtems/libio.h>
+#include <termios.h>
+#include <rtems/bspIo.h>
+
+/* Put the CPU (or UART) specific header file #include here */
+#include <mc9328mxl.h>
+#include <libchip/serial.h>
+#include <libchip/sersupp.h>
+
+/* How many serial ports? */
+#define NUM_DEVS 2
+
+int uart_poll_read(int minor);
+
+int dbg_dly;
+
+/* static function prototypes */
+static int uart_first_open(int major, int minor, void *arg);
+static int uart_last_close(int major, int minor, void *arg);
+static int uart_read(int minor);
+static int uart_write(int minor, const char *buf, int len);
+static void uart_init(int minor);
+static void uart_write_polled(int minor, char c);
+static int uart_set_attributes(int minor, const struct termios *t);
+
+/* These are used by code in console.c */
+unsigned long Console_Port_Count = NUM_DEVS;
+console_data Console_Port_Data[NUM_DEVS];
+
+/* rtems console uses the following minor number */
+rtems_device_minor_number Console_Port_Minor = 0;
+
+/* Pointers to functions for handling the UART. */
+console_fns uart_fns =
+{
+ libchip_serial_default_probe,
+ uart_first_open,
+ uart_last_close,
+ uart_read,
+ uart_write,
+ uart_init,
+ uart_write_polled, /* not used in this driver */
+ uart_set_attributes,
+ FALSE /* TRUE if interrupt driven, FALSE if not. */
+};
+
+/*
+ * There's one item in array for each UART.
+ *
+ * Some of these fields are marked "NOT USED". They are not used
+ * by console.c, but may be used by drivers in libchip
+ *
+ */
+console_tbl Console_Port_Tbl[] = {
+ {
+ "/dev/com0", /* sDeviceName */
+ SERIAL_CUSTOM, /* deviceType */
+ &uart_fns, /* pDeviceFns */
+ NULL, /* deviceProbe */
+ NULL, /* pDeviceFlow */
+ 0, /* ulMargin - NOT USED */
+ 0, /* ulHysteresis - NOT USED */
+ NULL, /* pDeviceParams */
+ 0, /* ulCtrlPort1 - NOT USED */
+ 0, /* ulCtrlPort2 - NOT USED */
+ 0, /* ulDataPort - NOT USED */
+ NULL, /* getRegister - NOT USED */
+ NULL, /* setRegister - NOT USED */
+ NULL, /* getData - NOT USED */
+ NULL, /* setData - NOT USED */
+ 0, /* ulClock - NOT USED */
+ 0 /* ulIntVector - NOT USED */
+ },
+ {
+ "/dev/com1", /* sDeviceName */
+ SERIAL_CUSTOM, /* deviceType */
+ &uart_fns, /* pDeviceFns */
+ NULL, /* deviceProbe */
+ NULL, /* pDeviceFlow */
+ 0, /* ulMargin - NOT USED */
+ 0, /* ulHysteresis - NOT USED */
+ NULL, /* pDeviceParams */
+ 0, /* ulCtrlPort1 - NOT USED */
+ 0, /* ulCtrlPort2 - NOT USED */
+ 0, /* ulDataPort - NOT USED */
+ NULL, /* getRegister - NOT USED */
+ NULL, /* setRegister - NOT USED */
+ NULL, /* getData - NOT USED */
+ NULL, /* setData - NOT USED */
+ 0, /* ulClock - NOT USED */
+ 0 /* ulIntVector - NOT USED */
+ }
+};
+
+/*********************************************************************/
+/* Functions called via termios callbacks (i.e. the ones in uart_fns */
+/*********************************************************************/
+
+/*
+ * This is called the first time each device is opened. If the driver
+ * is interrupt driven, you should enable interrupts here. Otherwise,
+ * it's probably safe to do nothing.
+ *
+ * Since micromonitor already set up the UART, we do nothing.
+ */
+static int uart_first_open(int major, int minor, void *arg)
+{
+ return 0;
+}
+
+
+/*
+ * This is called the last time each device is closed. If the driver
+ * is interrupt driven, you should disable interrupts here. Otherwise,
+ * it's probably safe to do nothing.
+ */
+static int uart_last_close(int major, int minor, void *arg)
+{
+ return 0;
+}
+
+
+/*
+ * Read one character from UART.
+ *
+ * Return -1 if there's no data, otherwise return
+ * the character in lowest 8 bits of returned int.
+ */
+static int uart_read(int minor)
+{
+ char c;
+
+ if (minor == 0) {
+ if (MC9328MXL_UART1_SR2 & MC9328MXL_UART_SR2_RDR) {
+ c = MC9328MXL_UART1_RXD & MC9328MXL_UART_RXD_CHARMASK;
+ return c;
+ } else {
+ return -1;
+ }
+ } else if (minor == 1) {
+ if (MC9328MXL_UART2_SR2 & MC9328MXL_UART_SR2_RDR) {
+ c = MC9328MXL_UART2_RXD & MC9328MXL_UART_RXD_CHARMASK;
+ return c;
+ } else {
+ return -1;
+ }
+ } else {
+ printk("Unknown console minor number: %d\n", minor);
+ return -1;
+ }
+
+}
+
+
+/*
+ * Write buffer to UART
+ *
+ * return 1 on success, -1 on error
+ */
+static int uart_write(int minor, const char *buf, int len)
+{
+ int i;
+
+ if (minor == 0) {
+ for (i = 0; i < len; i++) {
+ /* Wait for fifo to have room */
+ while(!(MC9328MXL_UART1_SR2 & MC9328MXL_UART_SR2_TXDC)) {
+ continue;
+ }
+
+ MC9328MXL_UART1_TXD = (char) buf[i];
+ }
+ } else if (minor == 1) {
+ for (i = 0; i < len; i++) {
+ /* Wait for fifo to have room */
+ while(!(MC9328MXL_UART2_SR2 & MC9328MXL_UART_SR2_TXDC)) {
+ continue;
+ }
+
+ MC9328MXL_UART2_TXD = (char) buf[i];
+ }
+ } else {
+ printk("Unknown console minor number: %d\n", minor);
+ return -1;
+ }
+
+ return 1;
+}
+
+
+/* Set up the UART. */
+static void uart_init(int minor)
+{
+ /* leave the debug sio port as setup by umon */
+}
+
+/* I'm not sure this is needed for the shared console driver. */
+static void uart_write_polled(int minor, char c)
+{
+ uart_write(minor, &c, 1);
+}
+
+/* This is for setting baud rate, bits, etc. */
+static int uart_set_attributes(int minor, const struct termios *t)
+{
+ return 0;
+}
+
+/***********************************************************************/
+/*
+ * The following functions are not used by TERMIOS, but other RTEMS
+ * functions use them instead.
+ */
+/***********************************************************************/
+/*
+ * Read from UART. This is used in the exit code, and can't
+ * rely on interrupts.
+*/
+int uart_poll_read(int minor)
+{
+ return uart_read(minor);
+}
+
+
+/*
+ * Write a character to the console. This is used by printk() and
+ * maybe other low level functions. It should not use interrupts or any
+ * RTEMS system calls. It needs to be very simple
+ */
+static void _BSP_put_char( char c ) {
+ uart_write_polled(0, c);
+ if (c == '\n') {
+ uart_write_polled(0, '\r');
+ }
+}
+
+BSP_output_char_function_type BSP_output_char = _BSP_put_char;
+
+
+
diff --git a/c/src/lib/libbsp/arm/csb336/include/bsp.h b/c/src/lib/libbsp/arm/csb336/include/bsp.h
new file mode 100644
index 0000000000..460456e225
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/include/bsp.h
@@ -0,0 +1,61 @@
+/*
+ * BSP CSB336 header file
+ *
+ * Copyright (c) 2004 Cogent Computer Systems
+ * Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ *
+ * $Id$
+*/
+#ifndef __BSP_H__
+#define __BSP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <bspopts.h>
+
+#include <rtems.h>
+#include <rtems/iosupp.h>
+#include <rtems/console.h>
+#include <rtems/clockdrv.h>
+#include <mc9328mxl.h>
+
+
+/* What is the input clock freq in hertz? */
+#define BSP_OSC_FREQ 16000000 /* 16 MHz oscillator */
+#define BSP_XTAL_FREQ 32768 /* 32.768 KHz crystal */
+
+/* How many serial ports? */
+#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
+
+/* How big should the interrupt stack be? */
+#define CONFIGURE_INTERRUPT_STACK_MEMORY (16 * 1024)
+
+extern rtems_configuration_table BSP_Configuration;
+
+int get_perclk1_freq(void);
+
+/*
+ * Network driver configuration
+ */
+extern struct rtems_bsdnet_ifconfig *config;
+
+/* Change these to match your board */
+int rtems_mc9328mxl_enet_attach(struct rtems_bsdnet_ifconfig *config,
+ void *chip);
+#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
+#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_mc9328mxl_enet_attach
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BSP_H__ */
+
diff --git a/c/src/lib/libbsp/arm/csb336/include/tm27.h b/c/src/lib/libbsp/arm/csb336/include/tm27.h
new file mode 100644
index 0000000000..b417668d83
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/include/tm27.h
@@ -0,0 +1,32 @@
+/*
+ * tm27.h
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * $Id$
+ */
+
+#ifndef _RTEMS_TMTEST27
+#error "This is an RTEMS internal file you must not include directly."
+#endif
+
+#ifndef __tm27_h
+#define __tm27_h
+
+/*
+ * Define the interrupt mechanism for Time Test 27
+ */
+
+#define MUST_WAIT_FOR_INTERRUPT 0
+
+#define Install_tm27_vector( handler ) /* empty */
+
+#define Cause_tm27_intr() /* empty */
+
+#define Clear_tm27_intr() /* empty */
+
+#define Lower_tm27_intr() /* empty */
+
+#endif
diff --git a/c/src/lib/libbsp/arm/csb336/network/lan91c11x.c b/c/src/lib/libbsp/arm/csb336/network/lan91c11x.c
new file mode 100644
index 0000000000..961746a636
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/network/lan91c11x.c
@@ -0,0 +1,267 @@
+/*
+ * Helper functions for SMSC LAN91C11x
+ *
+ * Copyright (c) 2004 by Cogent Computer Systems
+ * Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * $Id$
+ */
+#include <rtems.h>
+#include "lan91c11x.h"
+
+static rtems_interrupt_level level;
+
+void lan91c11x_lock(void)
+{
+ _CPU_ISR_Disable(level);
+}
+
+void lan91c11x_unlock(void)
+{
+ _CPU_ISR_Enable(level);
+}
+
+uint16_t lan91c11x_read_reg(int reg)
+{
+ volatile uint16_t *ptr = (uint16_t *)LAN91C11X_BASE_ADDR;
+ uint16_t old_bank;
+ uint16_t val;
+ rtems_interrupt_level level;
+
+ _CPU_ISR_Disable(level);
+
+ /* save the bank register */
+ old_bank = ptr[7] & 0x7;
+
+ /* set the bank register */
+ ptr[7] = (reg >> 4) & 0x7;
+
+ val = ptr[((reg & 0xf) >> 1)];
+
+ /* restore the bank register */
+ ptr[7] = old_bank;
+
+ _CPU_ISR_Enable(level);
+ return val;
+}
+
+void lan91c11x_write_reg(int reg, uint16_t value)
+{
+ volatile uint16_t *ptr = (uint16_t *)LAN91C11X_BASE_ADDR;
+ uint16_t old_bank;
+ rtems_interrupt_level level;
+
+ _CPU_ISR_Disable(level);
+
+ /* save the bank register */
+ old_bank = ptr[7] & 0x7;
+
+ /* set the bank register */
+ ptr[7] = (reg >> 4) & 0x7;
+
+ ptr[((reg & 0xf) >> 1)] = value;
+
+ /* restore the bank register */
+ ptr[7] = old_bank;
+
+ _CPU_ISR_Enable(level);
+}
+
+uint16_t lan91c11x_read_reg_fast(int reg)
+{
+ volatile uint16_t *ptr = (uint16_t *)LAN91C11X_BASE_ADDR;
+ uint16_t val;
+
+ val = ptr[((reg & 0xf) >> 1)];
+
+ return val;
+}
+
+void lan91c11x_write_reg_fast(int reg, uint16_t value)
+{
+ volatile uint16_t *ptr = (uint16_t *)LAN91C11X_BASE_ADDR;
+
+ ptr[((reg & 0xf) >> 1)] = value;
+}
+
+
+uint16_t lan91c11x_read_phy_reg(int reg)
+{
+ int i;
+ uint16_t mask;
+ uint16_t bits[64];
+ int clk_idx = 0;
+ int input_idx = 0;
+ uint16_t phydata;
+
+ /* 32 consecutive ones on MDO to establish sync */
+ for (i = 0; i < 32; ++i) {
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO;
+ }
+
+ /* Start code <01> */
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE;
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO;
+
+ /* Read command <10> */
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO;
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE;
+
+ /* Output the PHY address, msb first - Internal PHY is address 0 */
+ for (i = 0; i < 5; ++i) {
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE;
+ }
+
+ /* Output the phy register number, msb first */
+ mask = 0x10;
+ for (i = 0; i < 5; ++i) {
+ if (reg & mask) {
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO;
+ } else {
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE;
+ }
+
+
+ /* Shift to next lowest bit */
+ mask >>= 1;
+ }
+
+ /* 1 bit time for turnaround */
+ bits[clk_idx++] = 0;
+
+ /* Input starts at this bit time */
+ input_idx = clk_idx;
+
+ /* Will input 16 bits */
+ for (i = 0; i < 16; ++i) {
+ bits[clk_idx++] = 0;
+ }
+
+ /* Final clock bit */
+ bits[clk_idx++] = 0;
+
+ /* Turn off all MII Interface bits */
+ lan91c11x_write_reg(LAN91C11X_MGMT,
+ lan91c11x_read_reg(LAN91C11X_MGMT) & 0xfff0);
+
+ /* Clock all 64 cycles */
+ for (i = 0; i < sizeof bits; ++i) {
+ /* Clock Low - output data */
+ lan91c11x_write_reg(LAN91C11X_MGMT, bits[i]);
+ rtems_task_wake_after(1);
+
+ /* Clock Hi - input data */
+ lan91c11x_write_reg(LAN91C11X_MGMT, bits[i] | LAN91C11X_MGMT_MCLK);
+ rtems_task_wake_after(1);
+ bits[i] |= lan91c11x_read_reg(LAN91C11X_MGMT) & LAN91C11X_MGMT_MDI;
+ }
+
+ /* Return to idle state */
+ /* Set clock to low, data to low, and output tristated */
+ lan91c11x_write_reg(LAN91C11X_MGMT, lan91c11x_read_reg(LAN91C11X_MGMT) & 0xfff0);
+ rtems_task_wake_after(1);
+
+ /* Recover input data */
+ phydata = 0;
+ for (i = 0; i < 16; ++i) {
+ phydata <<= 1;
+
+ if (bits[input_idx++] & LAN91C11X_MGMT_MDI) {
+ phydata |= 0x0001;
+ }
+ }
+
+ return phydata;
+}
+
+
+
+void lan91c11x_write_phy_reg(int reg, uint16_t phydata)
+{
+ int i;
+ ushort mask;
+ ushort bits[64];
+ int clk_idx = 0;
+
+ /* 32 consecutive ones on MDO to establish sync */
+ for (i = 0; i < 32; ++i) {
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO;
+ }
+
+ /* Start code <01> */
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE;
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO;
+
+ /* Write command <01> */
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE;
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO;
+
+ /* Output the PHY address, msb first - Internal PHY is address 0 */
+ for (i = 0; i < 5; ++i) {
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE;
+ }
+
+ /* Output the phy register number, msb first */
+ mask = 0x10;
+ for (i = 0; i < 5; ++i) {
+ if (reg & mask) {
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO;
+ } else {
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE;
+ }
+
+ /* Shift to next lowest bit */
+ mask >>= 1;
+ }
+
+ /* 2 extra bit times for turnaround */
+ bits[clk_idx++] = 0;
+ bits[clk_idx++] = 0;
+
+ /* Write out 16 bits of data, msb first */
+ mask = 0x8000;
+ for (i = 0; i < 16; ++i) {
+ if (phydata & mask) {
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO;
+ } else {
+ bits[clk_idx++] = LAN91C11X_MGMT_MDOE;
+ }
+
+ /* Shift to next lowest bit */
+ mask >>= 1;
+ }
+
+ /* Final clock bit */
+ bits[clk_idx++] = 0;
+
+ /* Turn off all MII Interface bits */
+ lan91c11x_write_reg(LAN91C11X_MGMT,
+ lan91c11x_read_reg(LAN91C11X_MGMT) & 0xfff0);
+
+ /* Clock all 64 cycles */
+ for (i = 0; i < sizeof bits; ++i) {
+ /* Clock Low - output data */
+ lan91c11x_write_reg(LAN91C11X_MGMT, bits[i]);
+ rtems_task_wake_after(1);
+
+ /* Clock Hi - input data */
+ lan91c11x_write_reg(LAN91C11X_MGMT, bits[i] | LAN91C11X_MGMT_MCLK);
+ rtems_task_wake_after(1);
+ bits[i] |= lan91c11x_read_reg(LAN91C11X_MGMT) & LAN91C11X_MGMT_MDI;
+ }
+
+ /* Return to idle state */
+ /* Set clock to low, data to low, and output tristated */
+ lan91c11x_write_reg(LAN91C11X_MGMT,
+ lan91c11x_read_reg(LAN91C11X_MGMT) & 0xfff0);
+ rtems_task_wake_after(1);
+
+}
+
+
+
diff --git a/c/src/lib/libbsp/arm/csb336/network/lan91c11x.h b/c/src/lib/libbsp/arm/csb336/network/lan91c11x.h
new file mode 100644
index 0000000000..6f7d12a3b3
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/network/lan91c11x.h
@@ -0,0 +1,216 @@
+/*
+ * Header file for SMSC LAN91C11x ethernet devices
+ *
+ * Copyright (c) 2004 by Cogent Computer Systems
+ * Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * $Id$
+ */
+#ifndef __LAN91C11X_H__
+#define __LAN91C11X_H__
+
+#include <rtems.h>
+#include <bsp.h>
+
+uint16_t lan91c11x_read_reg(int);
+void lan91c11x_write_reg(int, uint16_t);
+uint16_t lan91c11x_read_reg_fast(int);
+void lan91c11x_write_reg_fast(int, uint16_t);
+void lan91c11x_write_phy_reg(int , uint16_t);
+uint16_t lan91c11x_read_phy_reg(int);
+void lan91c11x_unlock(void);
+void lan91c11x_lock(void);
+
+#define LAN91C11X_BASE_ADDR 0x12000000
+
+#define LAN91C11X_REG(_b_, _r_) ((((_b_) & 0xf) << 4) | ((_r_) & 0xf))
+
+
+#define LAN91C11X_TCR (LAN91C11X_REG(0, 0x0))
+#define LAN91C11X_EPHSTAT (LAN91C11X_REG(0, 0x2))
+#define LAN91C11X_RCR (LAN91C11X_REG(0, 0x4))
+#define LAN91C11X_CNTR (LAN91C11X_REG(0, 0x6))
+#define LAN91C11X_MIR (LAN91C11X_REG(0, 0x8))
+#define LAN91C11X_RPCR (LAN91C11X_REG(0, 0xa))
+#define LAN91C11X_BANK (LAN91C11X_REG(0, 0xe))
+#define LAN91C11X_CONFIG (LAN91C11X_REG(1, 0x0))
+#define LAN91C11X_BASE (LAN91C11X_REG(1, 0x2))
+#define LAN91C11X_IA0 (LAN91C11X_REG(1, 0x4))
+#define LAN91C11X_IA2 (LAN91C11X_REG(1, 0x6))
+#define LAN91C11X_IA4 (LAN91C11X_REG(1, 0x8))
+#define LAN91C11X_GNRL (LAN91C11X_REG(1, 0xa))
+#define LAN91C11X_CTRL (LAN91C11X_REG(1, 0xc))
+#define LAN91C11X_MMUCMD (LAN91C11X_REG(2, 0x0))
+#define LAN91C11X_PNR (LAN91C11X_REG(2, 0x2))
+#define LAN91C11X_FIFO (LAN91C11X_REG(2, 0x4))
+#define LAN91C11X_PTR (LAN91C11X_REG(2, 0x6))
+#define LAN91C11X_DATA (LAN91C11X_REG(2, 0x8))
+#define LAN91C11X_INT (LAN91C11X_REG(2, 0xc))
+#define LAN91C11X_MT0 (LAN91C11X_REG(3, 0x0))
+#define LAN91C11X_MT2 (LAN91C11X_REG(3, 0x2))
+#define LAN91C11X_MT4 (LAN91C11X_REG(3, 0x4))
+#define LAN91C11X_MT6 (LAN91C11X_REG(3, 0x6))
+#define LAN91C11X_MGMT (LAN91C11X_REG(3, 0x8))
+#define LAN91C11X_REV (LAN91C11X_REG(3, 0xa))
+#define LAN91C11X_ERCV (LAN91C11X_REG(3, 0xc))
+
+
+#define LAN91C11X_TCR_TXENA (bit(0))
+#define LAN91C11X_TCR_LOOP (bit(1))
+#define LAN91C11X_TCR_FORCOL (bit(2))
+#define LAN91C11X_TCR_PADEN (bit(7))
+#define LAN91C11X_TCR_NOCRC (bit(8))
+#define LAN91C11X_TCR_MONCSN (bit(10))
+#define LAN91C11X_TCR_FDUPLX (bit(11))
+#define LAN91C11X_TCR_STPSQET (bit(12))
+#define LAN91C11X_TCR_EPHLOOP (bit(13))
+#define LAN91C11X_TCR_SWFDUP (bit(15))
+
+#define LAN91C11X_EPHSTAT_TXSUC (bit(0))
+#define LAN91C11X_EPHSTAT_SNGLCOL (bit(1))
+#define LAN91C11X_EPHSTAT_MULCOL (bit(2))
+#define LAN91C11X_EPHSTAT_LTXMUL (bit(3))
+#define LAN91C11X_EPHSTAT_16COL (bit(4))
+#define LAN91C11X_EPHSTAT_SQET (bit(5))
+#define LAN91C11X_EPHSTAT_LTXBRD (bit(6))
+#define LAN91C11X_EPHSTAT_TXDFR (bit(7))
+#define LAN91C11X_EPHSTAT_LATCOL (bit(9))
+#define LAN91C11X_EPHSTAT_LOST (bit(10))
+#define LAN91C11X_EPHSTAT_EXCDEF (bit(11))
+#define LAN91C11X_EPHSTAT_CTRROL (bit(12))
+#define LAN91C11X_EPHSTAT_LINK (bit(14))
+#define LAN91C11X_EPHSTAT_TXUNRN (bit(15))
+
+#define LAN91C11X_RCR_RXABT (bit(0))
+#define LAN91C11X_RCR_PRMS (bit(1))
+#define LAN91C11X_RCR_ALMUL (bit(2))
+#define LAN91C11X_RCR_RXEN (bit(8))
+#define LAN91C11X_RCR_STRIP (bit(9))
+#define LAN91C11X_RCR_ABTENB (bit(13))
+#define LAN91C11X_RCR_FILT (bit(14))
+#define LAN91C11X_RCR_RST (bit(15))
+
+#define LAN91C11X_RPCR_LS0B (bit(2))
+#define LAN91C11X_RPCR_LS1B (bit(3))
+#define LAN91C11X_RPCR_LS2B (bit(4))
+#define LAN91C11X_RPCR_LS0A (bit(5))
+#define LAN91C11X_RPCR_LS1A (bit(6))
+#define LAN91C11X_RPCR_LS2A (bit(7))
+#define LAN91C11X_RPCR_ANEG (bit(11))
+#define LAN91C11X_RPCR_DPLX (bit(12))
+#define LAN91C11X_RPCR_SPEED (bit(13))
+
+#define LAN91C11X_CONFIG_EXTPHY (bit(9))
+#define LAN91C11X_CONFIG_GPCTRL (bit(10))
+#define LAN91C11X_CONFIG_NOWAIT (bit(12))
+#define LAN91C11X_CONFIG_PWR (bit(15))
+
+#define LAN91C11X_CTRL_STORE (bit(0))
+#define LAN91C11X_CTRL_RELOAD (bit(1))
+#define LAN91C11X_CTRL_EEPROM (bit(2))
+#define LAN91C11X_CTRL_TEEN (bit(5))
+#define LAN91C11X_CTRL_CREN (bit(6))
+#define LAN91C11X_CTRL_LEEN (bit(7))
+#define LAN91C11X_CTRL_AUTO (bit(11))
+#define LAN91C11X_CTRL_RCVBAD (bit(14))
+
+#define LAN91C11X_MMUCMD_BUSY (bit(0))
+#define LAN91C11X_MMUCMD_NOOP (0 << 5)
+#define LAN91C11X_MMUCMD_ALLOCTX (1 << 5)
+#define LAN91C11X_MMUCMD_RESETMMU (2 << 5)
+#define LAN91C11X_MMUCMD_REMFRM (3 << 5)
+#define LAN91C11X_MMUCMD_REMTOP (4 << 5)
+#define LAN91C11X_MMUCMD_RELEASE (5 << 5)
+#define LAN91C11X_MMUCMD_ENQUEUE (6 << 5)
+#define LAN91C11X_MMUCMD_RESETTX (7 << 5)
+
+#define LAN91C11X_PTR_MASK (0x7ff)
+#define LAN91C11X_PTR_NE (bit(11))
+#define LAN91C11X_PTR_ETEN (bit(12))
+#define LAN91C11X_PTR_READ (bit(13))
+#define LAN91C11X_PTR_AUTOINC (bit(14))
+#define LAN91C11X_PTR_RCV (bit(15))
+
+#define LAN91C11X_INT_RX (bit(0))
+#define LAN91C11X_INT_TX (bit(1))
+#define LAN91C11X_INT_TXE (bit(2))
+#define LAN91C11X_INT_ALLOC (bit(3))
+#define LAN91C11X_INT_RXOV (bit(4))
+#define LAN91C11X_INT_EPH (bit(5))
+#define LAN91C11X_INT_ERX (bit(6))
+#define LAN91C11X_INT_MD (bit(7))
+#define LAN91C11X_INT_RXMASK (bit(8))
+#define LAN91C11X_INT_TXMASK (bit(9))
+#define LAN91C11X_INT_TXEMASK (bit(10))
+#define LAN91C11X_INT_ALLOCMASK (bit(11))
+#define LAN91C11X_INT_RXOVMASK (bit(12))
+#define LAN91C11X_INT_EPHMASK (bit(13))
+#define LAN91C11X_INT_ERXMASK (bit(14))
+#define LAN91C11X_INT_MDMASK (bit(15))
+
+#define LAN91C11X_MGMT_MDO (bit(0))
+#define LAN91C11X_MGMT_MDI (bit(1))
+#define LAN91C11X_MGMT_MCLK (bit(2))
+#define LAN91C11X_MGMT_MDOE (bit(3))
+#define LAN91C11X_MGMT_MSKCRS100 (bit(14))
+
+
+#define LAN91C11X_PKT_CTRL_CRC (bit(4))
+#define LAN91C11X_PKT_CTRL_ODD (bit(5))
+
+
+/* PHY Registers */
+#define PHY_CTRL 0x00 /* PHY Control */
+#define PHY_STAT 0x01 /* PHY Status */
+#define PHY_ID1 0x02 /* PHY Identifier 1 */
+#define PHY_ID2 0x03 /* PHY Identifier 2 */
+#define PHY_AD 0x04 /* PHY Auto-negotiate Control */
+#define PHY_RMT 0x05 /* PHY Auto-neg Remote End Cap Register */
+#define PHY_CFG1 0x10 /* PHY Configuration 1 */
+#define PHY_CFG2 0x11 /* PHY Configuration 2 */
+#define PHY_INT 0x12 /* Status Output (Interrupt Status) */
+#define PHY_MASK 0x13 /* Interrupt Mask */
+
+/* PHY Control Register Bit Defines */
+#define PHY_CTRL_RST 0x8000 /* PHY Reset */
+#define PHY_CTRL_LPBK 0x4000 /* PHY Loopback */
+#define PHY_CTRL_SPEED 0x2000 /* 100Mbps, 0=10Mpbs */
+#define PHY_CTRL_ANEGEN 0x1000 /* Enable Auto negotiation */
+#define PHY_CTRL_PDN 0x0800 /* PHY Power Down mode */
+#define PHY_CTRL_MIIDIS 0x0400 /* MII 4 bit interface disabled */
+#define PHY_CTRL_ANEGRST 0x0200 /* Reset Auto negotiate */
+#define PHY_CTRL_DPLX 0x0100 /* Full Duplex, 0=Half Duplex */
+#define PHY_CTRL_COLTST 0x0080 /* MII Colision Test */
+
+#define PHY_STAT_CAPT4 0x8000
+#define PHY_STAT_CAPTXF 0x4000
+#define PHY_STAT_CAPTXH 0x2000
+#define PHY_STAT_CAPTF 0x1000
+#define PHY_STAT_CAPTH 0x0800
+#define PHY_STAT_CAPSUPR 0x0040
+#define PHY_STAT_ANEGACK 0x0020
+#define PHY_STAT_REMFLT 0x0010
+#define PHY_STAT_CAPANEG 0x0008
+#define PHY_STAT_LINK 0x0004
+#define PHY_STAT_JAB 0x0002
+#define PHY_STAT_EXREG 0x0001
+
+#define PHY_ADV_NP 0x8000
+#define PHY_ADV_ACK 0x4000
+#define PHY_ADV_RF 0x2000
+#define PHY_ADV_T4 0x0200
+#define PHY_ADV_TXFDX 0x0100
+#define PHY_ADV_TXHDX 0x0080
+#define PHY_ADV_10FDX 0x0040
+#define PHY_ADV_10HDX 0x0020
+#define PHY_ADV_CSMA 0x0001
+
+
+
+
+#endif /* __LAN91C11X_H__ */
diff --git a/c/src/lib/libbsp/arm/csb336/network/network.c b/c/src/lib/libbsp/arm/csb336/network/network.c
new file mode 100644
index 0000000000..0d63201f99
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/network/network.c
@@ -0,0 +1,724 @@
+/*
+ * MC9323MXL Ethernet driver
+ *
+ * Copyright (c) 2004 by Cogent Computer Systems
+ * Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * $Id$
+ */
+#include <rtems.h>
+#include <rtems/rtems_bsdnet.h>
+#include <mc9328mxl.h>
+#include "lan91c11x.h"
+
+#include <stdio.h>
+#include <string.h>
+
+#include <errno.h>
+#include <rtems/error.h>
+
+#include <sys/param.h>
+#include <sys/mbuf.h>
+#include <sys/socket.h>
+#include <sys/sockio.h>
+
+#include <net/if.h>
+
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+
+#include <irq.h>
+
+/* RTEMS event used by interrupt handler to start receive daemon. */
+#define START_RECEIVE_EVENT RTEMS_EVENT_1
+
+/* RTEMS event used to start transmit daemon. */
+#define START_TRANSMIT_EVENT RTEMS_EVENT_2
+
+static rtems_isr enet_isr(rtems_vector_number vector);
+static void enet_isr_on(const rtems_irq_connect_data *unused);
+static void enet_isr_off(const rtems_irq_connect_data *unused);
+static int enet_isr_is_on(const rtems_irq_connect_data *irq);
+
+/* Replace the first value with the clock's interrupt name. */
+rtems_irq_connect_data mc9328mxl_enet_isr_data = {BSP_INT_GPIO_PORTA,
+ (rtems_irq_hdl)enet_isr,
+ enet_isr_on,
+ enet_isr_off,
+ enet_isr_is_on,
+ 3, /* unused for ARM */
+ 0 }; /* unused for ARM */
+
+typedef struct {
+ unsigned long rx_packets; /* total packets received */
+ unsigned long tx_packets; /* total packets transmitted */
+ unsigned long rx_bytes; /* total bytes received */
+ unsigned long tx_bytes; /* total bytes transmitted */
+ unsigned long interrupts; /* total number of interrupts */
+ unsigned long rx_interrupts; /* total number of rx interrupts */
+ unsigned long tx_interrupts; /* total number of tx interrupts */
+ unsigned long txerr_interrupts; /* total number of tx error interrupts */
+
+} eth_stats_t;
+
+/*
+ * Hardware-specific storage
+ */
+typedef struct
+{
+ /*
+ * Connection to networking code
+ * This entry *must* be the first in the sonic_softc structure.
+ */
+ struct arpcom arpcom;
+
+ int accept_bcast;
+
+ /* Tasks waiting for interrupts */
+ rtems_id rx_task;
+ rtems_id tx_task;
+
+ eth_stats_t stats;
+
+} mc9328mxl_enet_softc_t;
+
+static mc9328mxl_enet_softc_t softc;
+
+
+/* function prototypes */
+int rtems_mc9328mxl_enet_attach(struct rtems_bsdnet_ifconfig *config,
+ void *chip);
+void mc9328mxl_enet_init(void *arg);
+void mc9328mxl_enet_init_hw(mc9328mxl_enet_softc_t *sc);
+void mc9328mxl_enet_start(struct ifnet *ifp);
+void mc9328mxl_enet_stop (mc9328mxl_enet_softc_t *sc);
+void mc9328mxl_enet_tx_task (void *arg);
+void mc9328mxl_enet_sendpacket (struct ifnet *ifp, struct mbuf *m);
+void mc9328mxl_enet_rx_task(void *arg);
+void mc9328mxl_enet_stats(mc9328mxl_enet_softc_t *sc);
+static int mc9328mxl_enet_ioctl(struct ifnet *ifp, int command, caddr_t data);
+
+
+int rtems_mc9328mxl_enet_attach (
+ struct rtems_bsdnet_ifconfig *config,
+ void *chip /* only one ethernet, so no chip number */
+ )
+{
+ struct ifnet *ifp;
+ int mtu;
+ int unitnumber;
+ char *unitname;
+ int tmp;
+
+ /*
+ * Parse driver name
+ */
+ unitnumber = rtems_bsdnet_parse_driver_name(config, &unitname);
+ if (unitnumber < 0) {
+ return 0;
+ }
+
+ /*
+ * Is driver free?
+ */
+ if (unitnumber != 0) {
+ printf ("Bad MC9328MXL unit number.\n");
+ return 0;
+ }
+
+ ifp = &softc.arpcom.ac_if;
+ if (ifp->if_softc != NULL) {
+ printf ("Driver already in use.\n");
+ return 0;
+ }
+
+ /* zero out the control structure */
+ memset( &softc, 0, sizeof(softc) );
+
+
+ /* set the MAC address */
+ tmp = lan91c11x_read_reg(LAN91C11X_IA0);
+ softc.arpcom.ac_enaddr[0] = tmp & 0xff;
+ softc.arpcom.ac_enaddr[1] = (tmp >> 8) & 0xff;
+
+ tmp = lan91c11x_read_reg(LAN91C11X_IA2);
+ softc.arpcom.ac_enaddr[2] = tmp & 0xff;
+ softc.arpcom.ac_enaddr[3] = (tmp >> 8) & 0xff;
+
+ tmp = lan91c11x_read_reg(LAN91C11X_IA4);
+ softc.arpcom.ac_enaddr[4] = tmp & 0xff;
+ softc.arpcom.ac_enaddr[5] = (tmp >> 8) & 0xff;
+
+ if (config->mtu) {
+ mtu = config->mtu;
+ } else {
+ mtu = ETHERMTU;
+ }
+
+ softc.accept_bcast = !config->ignore_broadcast;
+
+ /*
+ * Set up network interface values
+ */
+ ifp->if_softc = &softc;
+ ifp->if_unit = unitnumber;
+ ifp->if_name = unitname;
+ ifp->if_mtu = mtu;
+ ifp->if_init = mc9328mxl_enet_init;
+ ifp->if_ioctl = mc9328mxl_enet_ioctl;
+ ifp->if_start = mc9328mxl_enet_start;
+ ifp->if_output = ether_output;
+ ifp->if_flags = IFF_BROADCAST;
+ if (ifp->if_snd.ifq_maxlen == 0) {
+ ifp->if_snd.ifq_maxlen = ifqmaxlen;
+ }
+
+ /* Attach the interface */
+ if_attach (ifp);
+ ether_ifattach (ifp);
+ return 1;
+}
+
+void mc9328mxl_enet_init(void *arg)
+{
+ mc9328mxl_enet_softc_t *sc = arg;
+ struct ifnet *ifp = &sc->arpcom.ac_if;
+
+ /*
+ *This is for stuff that only gets done once (mc9328mxl_enet_init()
+ * gets called multiple times
+ */
+ if (sc->tx_task == 0)
+ {
+ /* Set up ENET hardware */
+ mc9328mxl_enet_init_hw(sc);
+
+ /* Start driver tasks */
+ sc->rx_task = rtems_bsdnet_newproc("ENrx",
+ 4096,
+ mc9328mxl_enet_rx_task,
+ sc);
+ sc->tx_task = rtems_bsdnet_newproc("ENtx",
+ 4096,
+ mc9328mxl_enet_tx_task,
+ sc);
+ } /* if tx_task */
+
+
+ /* Configure for promiscuous if needed */
+ if (ifp->if_flags & IFF_PROMISC) {
+ lan91c11x_write_reg(LAN91C11X_RCR,
+ (lan91c11x_read_reg(LAN91C11X_RCR) |
+ LAN91C11X_RCR_PRMS));
+ }
+
+
+ /*
+ * Tell the world that we're running.
+ */
+ ifp->if_flags |= IFF_RUNNING;
+
+ /* Enable TX/RX */
+ lan91c11x_write_reg(LAN91C11X_TCR,
+ (lan91c11x_read_reg(LAN91C11X_TCR) |
+ LAN91C11X_TCR_TXENA));
+
+ lan91c11x_write_reg(LAN91C11X_RCR,
+ (lan91c11x_read_reg(LAN91C11X_RCR) |
+ LAN91C11X_RCR_RXEN));
+
+
+} /* mc9328mxl_enet_init() */
+
+void mc9328mxl_enet_init_hw(mc9328mxl_enet_softc_t *sc)
+{
+ uint16_t stat;
+ uint16_t my = 0;
+
+ lan91c11x_write_reg(LAN91C11X_RCR, LAN91C11X_RCR_RST);
+ lan91c11x_write_reg(LAN91C11X_RCR, 0);
+ rtems_task_wake_after(1);
+
+ /* Reset the PHY */
+ lan91c11x_write_phy_reg(PHY_CTRL, PHY_CTRL_RST);
+ while(lan91c11x_read_phy_reg(PHY_CTRL) & PHY_CTRL_RST) {
+ rtems_task_wake_after(1);
+ }
+
+
+ stat = lan91c11x_read_phy_reg(PHY_STAT);
+
+ if(stat & PHY_STAT_CAPT4) {
+ my |= PHY_ADV_T4;
+ }
+/* 100Mbs doesn't work, so we won't advertise it */
+
+ if(stat & PHY_STAT_CAPTXF) {
+ my |= PHY_ADV_TXFDX;
+ }
+ if(stat & PHY_STAT_CAPTXH) {
+ my |= PHY_ADV_TXHDX;
+ }
+
+ if(stat & PHY_STAT_CAPTF) {
+ my |= PHY_ADV_10FDX;
+ }
+
+ if(stat & PHY_STAT_CAPTH) {
+ my |= PHY_ADV_10HDX;
+ }
+
+ my |= PHY_ADV_CSMA;
+
+ lan91c11x_write_phy_reg(PHY_AD, my);
+
+
+ /* Enable Autonegotiation */
+#if 0
+ lan91c11x_write_phy_reg(PHY_CTRL,
+ (PHY_CTRL_ANEGEN | PHY_CTRL_ANEGRST));
+#endif
+
+ /* Enable full duplex, let MAC take care
+ * of padding and CRC.
+ */
+ lan91c11x_write_reg(LAN91C11X_TCR,
+ (LAN91C11X_TCR_PADEN |
+ LAN91C11X_TCR_SWFDUP));
+
+ /* Disable promisc, don'tstrip CRC */
+ lan91c11x_write_reg(LAN91C11X_RCR, 0);
+
+ /* Enable auto-negotiation, LEDA is link, LEDB is traffic */
+ lan91c11x_write_reg(LAN91C11X_RPCR,
+ (LAN91C11X_RPCR_ANEG |
+ LAN91C11X_RPCR_LS2B));
+
+ /* Don't add wait states, enable PHY power */
+ lan91c11x_write_reg(LAN91C11X_CONFIG,
+ (LAN91C11X_CONFIG_NOWAIT |
+ LAN91C11X_CONFIG_PWR));
+
+ /* Disable error interrupts, enable auto release */
+ lan91c11x_write_reg(LAN91C11X_CTRL, LAN91C11X_CTRL_AUTO);
+
+ /* Reset MMU */
+ lan91c11x_write_reg(LAN91C11X_MMUCMD,
+ LAN91C11X_MMUCMD_RESETMMU );
+
+
+ rtems_task_wake_after(100);
+ /* Enable Autonegotiation */
+ lan91c11x_write_phy_reg(PHY_CTRL, 0x3000);
+ rtems_task_wake_after(100);
+
+ /* Enable Interrupts for RX */
+ lan91c11x_write_reg(LAN91C11X_INT, LAN91C11X_INT_RXMASK);
+
+ /* Enable interrupts on GPIO Port A3 */
+ /* Make pin 3 an input */
+ MC9328MXL_GPIOA_DDIR &= ~bit(3);
+
+ /* Use GPIO function for pin 3 */
+ MC9328MXL_GPIOA_GIUS |= bit(3);
+
+ /* Set for active high, level triggered interupt */
+ MC9328MXL_GPIOA_ICR1 = ((MC9328MXL_GPIOA_ICR1 & ~(3 << 6)) |
+ (2 << 6));
+
+ /* Enable GPIO port A3 interrupt */
+ MC9328MXL_GPIOA_IMR |= bit(3);
+
+ /* Install the interrupt handler */
+ BSP_install_rtems_irq_handler(&mc9328mxl_enet_isr_data);
+
+} /* mc9328mxl_enet_init_hw() */
+
+void mc9328mxl_enet_start(struct ifnet *ifp)
+{
+ mc9328mxl_enet_softc_t *sc = ifp->if_softc;
+
+ rtems_event_send(sc->tx_task, START_TRANSMIT_EVENT);
+ ifp->if_flags |= IFF_OACTIVE;
+}
+
+void mc9328mxl_enet_stop (mc9328mxl_enet_softc_t *sc)
+{
+ struct ifnet *ifp = &sc->arpcom.ac_if;
+
+ ifp->if_flags &= ~IFF_RUNNING;
+
+
+ /* Stop the transmitter and receiver. */
+ lan91c11x_write_reg(LAN91C11X_TCR,
+ (lan91c11x_read_reg(LAN91C11X_TCR) &
+ ~LAN91C11X_TCR_TXENA));
+
+ lan91c11x_write_reg(LAN91C11X_RCR,
+ (lan91c11x_read_reg(LAN91C11X_RCR) &
+ ~LAN91C11X_RCR_RXEN));
+
+}
+
+/*
+ * Driver transmit daemon
+ */
+void mc9328mxl_enet_tx_task(void *arg)
+{
+ mc9328mxl_enet_softc_t *sc = (mc9328mxl_enet_softc_t *)arg;
+ struct ifnet *ifp = &sc->arpcom.ac_if;
+ struct mbuf *m;
+ rtems_event_set events;
+
+ for (;;)
+ {
+ rtems_bsdnet_event_receive(
+ START_TRANSMIT_EVENT,
+ RTEMS_EVENT_ANY | RTEMS_WAIT,
+ RTEMS_NO_TIMEOUT,
+ &events);
+
+ /* Send packets till queue is empty */
+ for (;;)
+ {
+ /* Get the next mbuf chain to transmit. */
+ IF_DEQUEUE(&ifp->if_snd, m);
+ if (!m) {
+ break;
+ }
+ mc9328mxl_enet_sendpacket (ifp, m);
+ softc.stats.tx_packets++;
+
+ }
+ ifp->if_flags &= ~IFF_OACTIVE;
+ }
+}
+
+/* Send packet */
+void mc9328mxl_enet_sendpacket (struct ifnet *ifp, struct mbuf *m)
+{
+ struct mbuf *l = NULL;
+ int size = 0;
+ int tmp;
+ int i;
+ int start;
+ uint16_t d;
+
+ /* How big is the packet ? */
+ l = m;
+ do {
+ size += l->m_len;
+ l = l->m_next;
+ } while (l != NULL);
+
+ /* Allocate a TX buffer */
+ lan91c11x_write_reg(LAN91C11X_MMUCMD,
+ (LAN91C11X_MMUCMD_ALLOCTX |
+ (size >> 8)));
+
+ /* Wait for the allocation */
+ while ((lan91c11x_read_reg(LAN91C11X_INT) & LAN91C11X_INT_ALLOC) == 0) {
+ continue;
+ }
+
+ tmp = lan91c11x_read_reg(LAN91C11X_PNR);
+ lan91c11x_write_reg(LAN91C11X_PNR, ((tmp >> 8) & 0xff));
+
+ /* Set the data pointer for auto increment */
+ lan91c11x_write_reg(LAN91C11X_PTR, LAN91C11X_PTR_AUTOINC);
+
+ /* A delay is needed between pointer and data access ?!? */
+ for (i = 0; i < 10; i++) {
+ continue;
+ }
+
+ /* Write status word */
+ lan91c11x_write_reg(LAN91C11X_DATA, 0);
+
+ /* Write byte count */
+ if (size & 1) {
+ size++;
+ }
+ lan91c11x_write_reg(LAN91C11X_DATA, size + 6);
+
+ lan91c11x_lock();
+
+ /* Copy the mbuf */
+ l = m;
+ start = 0;
+ d = 0;
+ while (l != NULL)
+ {
+ uint8_t *data;
+
+ data = mtod(l, uint8_t *);
+
+ for (i = start; i < l->m_len; i++) {
+ if ((i & 1) == 0) {
+ d = data[i] << 8;
+ } else {
+ d = d | data[i];
+ lan91c11x_write_reg_fast(LAN91C11X_DATA, htons(d));
+ }
+ }
+
+ /* If everything is 2 byte aligned, i will be even */
+ start = (i & 1);
+
+ l = l->m_next;
+ }
+
+ /* write control byte */
+ if (i & 1) {
+ lan91c11x_write_reg_fast(LAN91C11X_DATA,
+ htons(LAN91C11X_PKT_CTRL_ODD | d));
+ } else {
+ lan91c11x_write_reg_fast(LAN91C11X_DATA, 0);
+ }
+
+ lan91c11x_unlock();
+
+ /* Enable TX interrupts */
+ lan91c11x_write_reg(LAN91C11X_INT,
+ (lan91c11x_read_reg(LAN91C11X_INT) |
+ LAN91C11X_INT_TXMASK |
+ LAN91C11X_INT_TXEMASK));
+
+ /* Enqueue it */
+ lan91c11x_write_reg(LAN91C11X_MMUCMD,
+ LAN91C11X_MMUCMD_ENQUEUE);
+
+ /* free the mbuf chain we just copied */
+ m_freem(m);
+
+} /* mc9328mxl_enet_sendpacket () */
+
+
+/* reader task */
+void mc9328mxl_enet_rx_task(void *arg)
+{
+ mc9328mxl_enet_softc_t *sc = (mc9328mxl_enet_softc_t *)arg;
+ struct ifnet *ifp = &sc->arpcom.ac_if;
+ struct mbuf *m;
+ struct ether_header *eh;
+ rtems_event_set events;
+ int pktlen;
+ uint16_t rsw;
+ uint16_t bc;
+ uint16_t cbyte;
+ int i;
+ uint16_t int_reg;
+
+ /* Input packet handling loop */
+ while (1) {
+ rtems_bsdnet_event_receive(
+ START_RECEIVE_EVENT,
+ RTEMS_EVENT_ANY | RTEMS_WAIT,
+ RTEMS_NO_TIMEOUT,
+ &events);
+
+ /* Configure for reads from RX data area */
+ lan91c11x_write_reg(LAN91C11X_PTR,
+ (LAN91C11X_PTR_AUTOINC |
+ LAN91C11X_PTR_RCV |
+ LAN91C11X_PTR_READ));
+
+ /* read the receive status word */
+ rsw = lan91c11x_read_reg(LAN91C11X_DATA);
+ /* TBD: Need to check rsw here */
+
+ /* read the byte count */
+ bc = lan91c11x_read_reg(LAN91C11X_DATA);
+ pktlen = (bc & 0x7ff) - 6;
+
+ /* get an mbuf for this packet */
+ MGETHDR(m, M_WAIT, MT_DATA);
+
+ /* now get a cluster pointed to by the mbuf */
+ /* since an mbuf by itself is too small */
+ MCLGET(m, M_WAIT);
+
+ lan91c11x_lock();
+
+ /* Copy the received packet into an mbuf */
+ for (i = 0; i < (pktlen / 2); i++) {
+ ((uint16_t*)m->m_ext.ext_buf)[i] =
+ lan91c11x_read_reg_fast(LAN91C11X_DATA);
+ }
+
+ cbyte = lan91c11x_read_reg_fast(LAN91C11X_DATA);
+ if (cbyte & LAN91C11X_PKT_CTRL_ODD) {
+ ((uint16_t*)m->m_ext.ext_buf)[i] = cbyte;
+ pktlen++;
+ }
+ lan91c11x_unlock();
+
+ /* Release the packets memory */
+ lan91c11x_write_reg(LAN91C11X_MMUCMD,
+ LAN91C11X_MMUCMD_REMTOP);
+
+ /* set the receiving interface */
+ m->m_pkthdr.rcvif = ifp;
+ m->m_nextpkt = 0;
+
+ /* set the length of the mbuf */
+ m->m_len = pktlen - (sizeof(struct ether_header));
+ m->m_pkthdr.len = m->m_len;
+
+ /* strip off the ethernet header from the mbuf */
+ /* but save the pointer to it */
+ eh = mtod (m, struct ether_header *);
+ m->m_data += sizeof(struct ether_header);
+
+
+ softc.stats.rx_packets++;
+
+ /* give all this stuff to the stack */
+ ether_input(ifp, eh, m);
+
+ /* renable RX interrupts */
+ int_reg = lan91c11x_read_reg(LAN91C11X_INT);
+ int_reg |= LAN91C11X_INT_RXMASK;
+ lan91c11x_write_reg(LAN91C11X_INT, int_reg);
+
+ }
+} /* mc9328mxl_enet_rx_task */
+
+
+/* Show interface statistics */
+void mc9328mxl_enet_stats (mc9328mxl_enet_softc_t *sc)
+{
+ printf (" Total Interrupts:%-8lu", sc->stats.interrupts);
+ printf (" Rx Interrupts:%-8lu", sc->stats.rx_interrupts);
+ printf (" Tx Interrupts:%-8lu\n", sc->stats.tx_interrupts);
+ printf (" Tx Error Interrupts:%-8lu\n", sc->stats.txerr_interrupts);
+ printf (" Rx Packets:%-8lu", sc->stats.rx_packets);
+ printf (" Tx Packets:%-8lu\n", sc->stats.tx_packets);
+}
+
+
+/* Enables mc9328mxl_enet interrupts. */
+static void enet_isr_on(const rtems_irq_connect_data *unused)
+{
+ /* Enable interrupts */
+ MC9328MXL_AITC_INTENNUM = MC9328MXL_INT_GPIO_PORTA;
+
+ return;
+}
+
+/* Disables enet interrupts */
+static void enet_isr_off(const rtems_irq_connect_data *unused)
+{
+ /* disable all various TX/RX interrupts */
+ MC9328MXL_AITC_INTDISNUM = MC9328MXL_INT_GPIO_PORTA;
+
+ return;
+}
+
+/* Tests to see if mc9328mxl_enet interrupts are enabled, and returns non-0 if so.
+ * If interrupt is not enabled, returns 0.
+ */
+static int enet_isr_is_on(const rtems_irq_connect_data *irq)
+{
+ return MC9328MXL_AITC_INTENABLEL & (1 << MC9328MXL_INT_GPIO_PORTA);
+}
+
+/* Driver ioctl handler */
+static int
+mc9328mxl_enet_ioctl (struct ifnet *ifp, int command, caddr_t data)
+{
+ mc9328mxl_enet_softc_t *sc = ifp->if_softc;
+ int error = 0;
+
+ switch (command) {
+ case SIOCGIFADDR:
+ case SIOCSIFADDR:
+ ether_ioctl (ifp, command, data);
+ break;
+
+ case SIOCSIFFLAGS:
+ switch (ifp->if_flags & (IFF_UP | IFF_RUNNING))
+ {
+ case IFF_RUNNING:
+ mc9328mxl_enet_stop (sc);
+ break;
+
+ case IFF_UP:
+ mc9328mxl_enet_init (sc);
+ break;
+
+ case IFF_UP | IFF_RUNNING:
+ mc9328mxl_enet_stop (sc);
+ mc9328mxl_enet_init (sc);
+ break;
+
+ default:
+ break;
+ } /* switch (if_flags) */
+ break;
+
+ case SIO_RTEMS_SHOW_STATS:
+ mc9328mxl_enet_stats (sc);
+ break;
+
+ /*
+ * FIXME: All sorts of multicast commands need to be added here!
+ */
+ default:
+ error = EINVAL;
+ break;
+ } /* switch (command) */
+ return error;
+}
+
+/* interrupt handler */
+rtems_isr enet_isr (rtems_vector_number v)
+{
+ uint16_t int_reg;
+
+ softc.stats.interrupts++;
+ /* get the ISR status and determine RX or TX */
+ int_reg = lan91c11x_read_reg(LAN91C11X_INT);
+
+ /* Handle RX interrupts */
+ if ((int_reg & LAN91C11X_INT_RX) && (int_reg & LAN91C11X_INT_RXMASK)) {
+ softc.stats.rx_interrupts++;
+
+ /* Disable the interrupt */
+ int_reg &= ~LAN91C11X_INT_RXMASK;
+
+ rtems_event_send (softc.rx_task, START_RECEIVE_EVENT);
+ }
+
+ /* Handle TX Empty interrupts */
+ if ((int_reg & LAN91C11X_INT_TXE) && (int_reg & LAN91C11X_INT_TXEMASK)) {
+ softc.stats.tx_interrupts++;
+
+ /* Disable the interrupt */
+ int_reg &= ~LAN91C11X_INT_TXEMASK;
+
+ /* Acknowledge the interrupt */
+ int_reg |= LAN91C11X_INT_TXE;
+
+ rtems_event_send(softc.tx_task, START_TRANSMIT_EVENT);
+
+ }
+
+ /* Handle interrupts for transmit errors */
+ if ((int_reg & LAN91C11X_INT_TX) && (int_reg & LAN91C11X_INT_TXMASK)) {
+ softc.stats.txerr_interrupts++;
+ printk("Caught TX interrupt - error on transmission\n");
+ }
+
+ /* Update the interrupt register on the 91c11x */
+ lan91c11x_write_reg(LAN91C11X_INT, int_reg);
+
+ /* clear GPIO Int. status */
+ MC9328MXL_GPIOA_ISR |= bit(3);
+}
+
diff --git a/c/src/lib/libbsp/arm/csb336/start/start.S b/c/src/lib/libbsp/arm/csb336/start/start.S
new file mode 100644
index 0000000000..1dc6f3d205
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/start/start.S
@@ -0,0 +1,147 @@
+/*
+ * Cogent CSB336 startup code
+ *
+ * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ *
+ * $Id$
+ */
+
+
+/* Some standard definitions...*/
+.equ PSR_MODE_USR, 0x10
+.equ PSR_MODE_FIQ, 0x11
+.equ PSR_MODE_IRQ, 0x12
+.equ PSR_MODE_SVC, 0x13
+.equ PSR_MODE_ABT, 0x17
+.equ PSR_MODE_UNDEF, 0x1B
+.equ PSR_MODE_SYS, 0x1F
+
+.equ PSR_I, 0x80
+.equ PSR_F, 0x40
+.equ PSR_T, 0x20
+
+.text
+.globl _start
+_start:
+ /*
+ * Since I don't plan to return to the bootloader,
+ * I don't have to save the registers.
+ *
+ * I'll just set the CPSR for SVC mode, interrupts
+ * off, and ARM instructions.
+ */
+ mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
+ msr cpsr, r0
+
+ /* zero the bss */
+ ldr r1, =_bss_end_
+ ldr r0, =_bss_start_
+
+_bss_init:
+ mov r2, #0
+ cmp r0, r1
+ strlot r2, [r0], #4
+ blo _bss_init /* loop while r0 < r1 */
+
+
+ /* --- Initialize stack pointer registers */
+ /* Enter IRQ mode and set up the IRQ stack pointer */
+ mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */
+ msr cpsr, r0
+ ldr r1, =_irq_stack_size
+ ldr sp, =_irq_stack
+ add sp, sp, r1
+
+ /* Enter FIQ mode and set up the FIQ stack pointer */
+ mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */
+ msr cpsr, r0
+ ldr r1, =_fiq_stack_size
+ ldr sp, =_fiq_stack
+ add sp, sp, r1
+
+ /* Enter ABT mode and set up the ABT stack pointer */
+ mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */
+ msr cpsr, r0
+ ldr r1, =_abt_stack_size
+ ldr sp, =_abt_stack
+ add sp, sp, r1
+
+ /* Set up the SVC stack pointer last and stay in SVC mode */
+ mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */
+ msr cpsr, r0
+ ldr r1, =_svc_stack_size
+ ldr sp, =_svc_stack
+ add sp, sp, r1
+ sub sp, sp, #0x64
+
+ /*
+ * Initialize the MMU. After we return, the MMU is enabled,
+ * and memory may be remapped. I hope we don't remap this
+ * memory away.
+ */
+ ldr r0, =mem_map
+ bl mmu_init
+
+ /*
+ * Initialize the exception vectors. This includes the
+ * exceptions vectors (0x00000000-0x0000001c), and the
+ * pointers to the exception handlers (0x00000020-0x0000003c).
+ */
+ mov r0, #0
+ adr r1, vector_block
+ ldmia r1!, {r2-r9}
+ stmia r0!, {r2-r9}
+ ldmia r1!, {r2-r9}
+ stmia r0!, {r2-r9}
+
+ /* Now we are prepared to start the BSP's C code */
+ bl boot_card
+
+ /*
+ * Theoretically, we could return to what started us up,
+ * but we'd have to have saved the registers and stacks.
+ * Instead, we'll just reset.
+ */
+ bl bsp_reset
+
+ /* We shouldn't get here. If we do, hang */
+_hang: b _hang
+
+
+/*
+ * This is the exception vector table and the pointers to
+ * the functions that handle the exceptions. It's a total
+ * of 16 words (64 bytes)
+ */
+vector_block:
+ ldr pc, Reset_Handler
+ ldr pc, Undefined_Handler
+ ldr pc, SWI_Handler
+ ldr pc, Prefetch_Handler
+ ldr pc, Abort_Handler
+ nop
+ ldr pc, IRQ_Handler
+ ldr pc, FIQ_Handler
+
+Reset_Handler: b bsp_reset
+Undefined_Handler: b Undefined_Handler
+SWI_Handler: b SWI_Handler
+Prefetch_Handler: b Prefetch_Handler
+Abort_Handler: b Abort_Handler
+ nop
+IRQ_Handler: b IRQ_Handler
+FIQ_Handler: b FIQ_Handler
+
+.globl Reset_Handler
+.globl Undefined_Handler
+.globl SWI_Handler
+.globl Prefetch_Handler
+.globl Abort_Handler
+.globl IRQ_Handler
+.globl FIQ_Handler
diff --git a/c/src/lib/libbsp/arm/csb336/startup/bspstart.c b/c/src/lib/libbsp/arm/csb336/startup/bspstart.c
new file mode 100644
index 0000000000..991c54177b
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/startup/bspstart.c
@@ -0,0 +1,233 @@
+/*
+ * Cogent CSB336 - MC9328MXL SBC startup code
+ *
+ * Copyright (c) 2004 by Cogent Computer Systems
+ * Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * $Id$
+ */
+#include <bsp.h>
+#include <rtems/libcsupport.h>
+#include <rtems/libio.h>
+#include <mc9328mxl.h>
+
+/* Global Variables */
+extern void *_flash_size;
+extern void *_flash_base;
+extern void *_sdram_size;
+extern void *_sdram_base;
+extern void *_bss_free_start;
+
+unsigned long free_mem_start;
+unsigned long free_mem_end;
+
+rtems_configuration_table BSP_Configuration;
+
+rtems_cpu_table Cpu_table;
+char *rtems_progname = "RTEMS";
+
+extern void rtems_irq_mngt_init(void);
+void bsp_libc_init( void *, unsigned32, int );
+void bsp_postdriver_hook(void);
+
+/**************************************************************************/
+/* */
+/* NAME: bsp_pretasking_hook - Function to setup system before startup */
+/* */
+/* DESCRIPTION: */
+/* This function is called before drivers are initialized and used */
+/* to setup libc and BSP extensions. */
+/* */
+/* RESTRICTIONS/LIMITATIONS: */
+/* Since this function is setting up libc, it cannot use and libc */
+/* functions. */
+/* */
+/**************************************************************************/
+void bsp_pretasking_hook(void)
+{
+ unsigned32 heap_start;
+ unsigned32 heap_size;
+
+ /*
+ * Set up the heap.
+ */
+ heap_start = free_mem_start;
+ heap_size = free_mem_end - free_mem_start;
+
+ /* call rtems lib init - malloc stuff */
+ bsp_libc_init((void *)heap_start, heap_size, 0);
+
+#ifdef RTEMS_DEBUG
+
+ rtems_debug_enable(RTEMS_DEBUG_ALL_MASK);
+
+#endif /* RTEMS_DEBUG */
+
+}
+
+
+/**************************************************************************/
+/* */
+/* NAME: bsp_start_default - BSP initialization function */
+/* */
+/* DESCRIPTION: */
+/* This function is called before RTEMS is initialized and used */
+/* adjust the kernel's configuration. */
+/* */
+/* This function also configures the CPU's memory protection unit. */
+/* */
+/* RESTRICTIONS/LIMITATIONS: */
+/* Since RTEMS is not configured, no RTEMS functions can be called. */
+/* */
+/**************************************************************************/
+void bsp_start_default( void )
+{
+
+ /* disable interrupts */
+ MC9328MXL_AITC_INTENABLEL = 0;
+ MC9328MXL_AITC_INTENABLEH = 0;
+
+ /* Set interrupt priority to -1 (allow all priorities) */
+ MC9328MXL_AITC_NIMASK = 0x1f;
+
+ /* tell rtems about the hooks we are using */
+ Cpu_table.pretasking_hook = bsp_pretasking_hook;
+ Cpu_table.postdriver_hook = bsp_postdriver_hook;
+
+ /* tell rtems to clear the workspace by default */
+ Cpu_table.do_zero_of_workspace = TRUE;
+
+ /* Place RTEMS workspace at beginning of free memory. */
+ BSP_Configuration.work_space_start = (void *)&_bss_free_start;
+
+ free_mem_start = ((unsigned32)&_bss_free_start +
+ BSP_Configuration.work_space_size);
+
+ free_mem_end = ((unsigned32)&_sdram_base + (unsigned32)&_sdram_size);
+
+
+ /*
+ * Init rtems exceptions management
+ */
+ rtems_exception_init_mngt();
+
+ /*
+ * Init rtems interrupt management
+ */
+ rtems_irq_mngt_init();
+
+
+ /*
+ * The following information is very useful when debugging.
+ */
+#if 0
+ printk( "work_space_size = 0x%x\n",
+ BSP_Configuration.work_space_size );
+ printk( "maximum_extensions = 0x%x\n",
+ BSP_Configuration.maximum_extensions );
+ printk( "microseconds_per_tick = 0x%x\n",
+ BSP_Configuration.microseconds_per_tick );
+ printk( "ticks_per_timeslice = 0x%x\n",
+ BSP_Configuration.ticks_per_timeslice );
+ printk( "maximum_devices = 0x%x\n",
+ BSP_Configuration.maximum_devices );
+ printk( "number_of_device_drivers = 0x%x\n",
+ BSP_Configuration.number_of_device_drivers );
+ printk( "Device_driver_table = 0x%x\n",
+ BSP_Configuration.Device_driver_table );
+ printk( "work_space_start = 0x%x\n",
+ BSP_Configuration.work_space_start );
+ printk( "work_space_size = 0x%x\n",
+ BSP_Configuration.work_space_size );
+#endif
+} /* bsp_start */
+
+
+
+/* Calcuate the frequency for perclk1 */
+int get_perclk1_freq(void)
+{
+ int fin;
+ int fpll;
+ int pd;
+ int mfd;
+ int mfi;
+ int mfn;
+ uint32_t reg;
+ int perclk1;
+
+ if (MC9328MXL_PLL_CSCR & MC9328MXL_PLL_CSCR_SYSSEL) {
+ /* Use external oscillator */
+ fin = BSP_OSC_FREQ;
+ } else {
+ /* Use scaled xtal freq */
+ fin = BSP_XTAL_FREQ * 512;
+ }
+
+ /* calculate the output of the system PLL */
+ reg = MC9328MXL_PLL_SPCTL0;
+ pd = ((reg & MC9328MXL_PLL_SPCTL_PD_MASK) >>
+ MC9328MXL_PLL_SPCTL_PD_SHIFT);
+ mfd = ((reg & MC9328MXL_PLL_SPCTL_MFD_MASK) >>
+ MC9328MXL_PLL_SPCTL_MFD_SHIFT);
+ mfi = ((reg & MC9328MXL_PLL_SPCTL_MFI_MASK) >>
+ MC9328MXL_PLL_SPCTL_MFI_SHIFT);
+ mfn = ((reg & MC9328MXL_PLL_SPCTL_MFN_MASK) >>
+ MC9328MXL_PLL_SPCTL_MFN_SHIFT);
+
+#if 0
+ printk("fin = %d\n", fin);
+ printk("pd = %d\n", pd);
+ printk("mfd = %d\n", mfd);
+ printk("mfi = %d\n", mfi);
+ printk("mfn = %d\n", mfn);
+ printk("(fin * mfi) / (pd + 1) = %d\n", (fin * mfi) / (pd + 1));
+ printk("(fin * mfn) / ((pd + 1) * (mfd + 1)) = %d\n",
+ (fin * mfn) / ((pd + 1) * (mfd + 1)));
+#endif
+
+ fpll = 2 * ( ((fin * mfi) / (pd + 1)) +
+ ((fin * mfn) / ((pd + 1) * (mfd + 1))) );
+
+ /* calculate the output of the PERCLK1 divider */
+ reg = MC9328MXL_PLL_PCDR;
+ perclk1 = fpll / (1 + ((reg & MC9328MXL_PLL_PCDR_PCLK1_MASK) >>
+ MC9328MXL_PLL_PCDR_PCLK1_SHIFT));
+
+ return perclk1;
+}
+
+/*
+ * By making this a weak alias for bsp_start_default, a brave soul
+ * can override the actual bsp_start routine used.
+ */
+
+void bsp_start (void) __attribute__ ((weak, alias("bsp_start_default")));
+
+
+/**
+ * Reset the system.
+ *
+ * This functions enables the watchdog and waits for it to
+ * fire, thus resetting the system.
+ */
+/**
+ * Reset the system.
+ *
+ * This functions enables the watchdog and waits for it to
+ * fire, thus resetting the system.
+ */
+void bsp_reset(void)
+{
+ rtems_interrupt_level level;
+
+ _CPU_ISR_Disable(level);
+
+ printk("\n\rI should reset here.\n\r");
+ while(1);
+}
diff --git a/c/src/lib/libbsp/arm/csb336/startup/exit.c b/c/src/lib/libbsp/arm/csb336/startup/exit.c
new file mode 100644
index 0000000000..7c546bc4bb
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/startup/exit.c
@@ -0,0 +1,36 @@
+/*
+ * Cogent CSB336 Shutdown code
+ *
+ * Copyright (c) 2004 by Cogent Computer Systems
+ * Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * $Id$
+ */
+#include <stdio.h>
+#include <bsp.h>
+#include <rtems/bspIo.h>
+#include <rtems/libio.h>
+
+int uart_poll_read(int);
+void BSP_reset();
+
+void bsp_cleanup(void)
+{
+ static char line[]="\nEXECUTIVE SHUTDOWN! Any key to reboot...";
+ /*
+ * AT this point, the console driver is disconnected => we must
+ * use polled output/input. This is exactly what printk
+ * does.
+ */
+ printk("\n");
+ printk(line);
+ while (uart_poll_read(0) < 0) continue;
+
+ bsp_reset();
+
+}
diff --git a/c/src/lib/libbsp/arm/csb336/startup/linkcmds b/c/src/lib/libbsp/arm/csb336/startup/linkcmds
new file mode 100644
index 0000000000..33020e02bc
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/startup/linkcmds
@@ -0,0 +1,240 @@
+/*
+ * Cogent CSB336 Linker script
+ *
+ * Copyright (c) 2004 by Cogent Computer Systems
+ * Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * $Id$
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+ "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+/* SEARCH_DIR(/usr/local/rtems-arm-dev-tools/arm-rtems/lib); */
+
+
+MEMORY {
+ sdram : ORIGIN = 0x08200000, LENGTH = 30M
+}
+
+/*
+ * Declare some sizes.
+ */
+
+/* The base for SDRAM is set to umon's APPRAMBASE */
+_sdram_base = DEFINED(_sdram_base) ? _sdram_base : 0x08200000;
+_sdram_size = DEFINED(_sdram_size) ? _sdram_size : 30M;
+
+
+_irq_stack_size = DEFINED(_irq_stack_size) ? _irq_stack_size : 0x1000;
+_fiq_stack_size = DEFINED(_fiq_stack_size) ? _fiq_stack_size : 0x400;
+_abt_stack_size = DEFINED(_abt_stack_size) ? _abt_stack_size : 0x100;
+_svc_stack_size = DEFINED(_svc_stack_size) ? _svc_stack_size : 0x1000;
+
+
+
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+
+SECTIONS
+{
+ .base :
+ {
+ arm_exception_table = .;
+
+ arm_reset_vect = .; /* 0x00 */
+ . += 4;
+
+ arm_undef_vect = .; /* 0x04 */
+ . += 4;
+
+ arm_swi_vect = .; /* 0x08 */
+ . += 4;
+
+ arm_iabrt_vect = .; /* 0x0c */
+ . += 4;
+
+ arm_dabrt_vect = .; /* 0x10 */
+ . += 4;
+
+ /* no vector here */
+ . += 4;
+
+ arm_irq_vect = .; /* 0x18 */
+ . += 4;
+
+ arm_fiq_vect = .; /* 0x1c */
+ . += 4;
+ /* FIXME: */
+
+ rtems_vector_table = .;
+ . += (8 * 4); /* 8 ARM interrupts */
+
+ bsp_vector_table = .;
+ . += (64 * 4); /* 64 MC9328MXL interrupts */
+
+ . = ALIGN (0x100);
+
+
+ } > sdram
+
+ .init :
+ {
+ KEEP (*(.init))
+ } > sdram /*=0*/
+
+ .text :
+ {
+ _text_start = .;
+ CREATE_OBJECT_SYMBOLS
+ *(.text)
+ *(.text.*)
+
+ /*
+ * Special FreeBSD sysctl sections.
+ */
+ . = ALIGN (16);
+ __start_set_sysctl_set = .;
+ *(set_sysctl_*);
+ __stop_set_sysctl_set = ABSOLUTE(.);
+ *(set_domain_*);
+ *(set_pseudo_*);
+
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ *(.gnu.linkonce.t*)
+ *(.glue_7)
+ *(.glue_7t)
+
+ /* I think these come from the ld docs: */
+ ___CTOR_LIST__ = .;
+ LONG((___CTOR_END__ - ___CTOR_LIST__) / 4 - 2)
+ *(.ctors)
+ LONG(0)
+ ___CTOR_END__ = .;
+ ___DTOR_LIST__ = .;
+ LONG((___DTOR_END__ - ___DTOR_LIST__) / 4 - 2)
+ *(.dtors)
+ LONG(0)
+ ___DTOR_END__ = .;
+
+ _etext = .;
+ PROVIDE (etext = .);
+ } > sdram
+
+ .fini :
+ {
+ KEEP (*(.fini))
+ } > sdram /*=0*/
+
+ .data :
+ {
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d*)
+ *(.jcr)
+ SORT(CONSTRUCTORS)
+ _edata = .;
+ } > sdram
+
+ .eh_frame : { *(.eh_frame) } > RAM
+ .data1 : { *(.data1) } > RAM
+ .eh_frame : { *(.eh_frame) } > RAM
+ .gcc_except_table : { *(.gcc_except_table) } > RAM
+
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata.*)
+ *(.gnu.linkonce.r*)
+ } > sdram
+
+ .bss :
+ {
+ _bss_start_ = .;
+ _clear_start = .;
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(64);
+ _clear_end = .;
+
+ . = ALIGN (256);
+ _abt_stack = .;
+ . += _abt_stack_size;
+
+ . = ALIGN (256);
+ _irq_stack = .;
+ . += _irq_stack_size;
+
+ . = ALIGN (256);
+ _fiq_stack = .;
+ . += _fiq_stack_size;
+
+ . = ALIGN (256);
+ _svc_stack = .;
+ . += _svc_stack_size;
+
+ _bss_end_ = .;
+ _end = .;
+ __end = .;
+
+/*
+ * Ideally, the MMU's translation table would be in SRAM. But we
+ * don't have any. If we don't use more regions than TLB entries (64),
+ * the lookup will only happen once for each region.
+ */
+ . = ALIGN (16 * 1024);
+ _ttbl_base = .;
+ . += (16 * 1024);
+
+ . = ALIGN (1024);
+ _bss_free_start = .;
+
+ } > sdram
+
+
+/* Debugging stuff follows? */
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /*.stack 0x80000 : { _stack = .; *(.stack) }*/
+ /* These must appear regardless of . */
+}
+
diff --git a/c/src/lib/libbsp/arm/csb336/startup/memmap.c b/c/src/lib/libbsp/arm/csb336/startup/memmap.c
new file mode 100644
index 0000000000..d76b8e18e8
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/startup/memmap.c
@@ -0,0 +1,34 @@
+/*
+ * CSB336 Memory Map
+ *
+ * Copyright (c) 2004 by Cogent Computer Systems
+ * Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * $Id$
+ */
+#include <rtems.h>
+#include <libcpu/mmu.h>
+
+/* Remember, the ARM920 has 64 TLBs. If you have more 1MB sections than
+ * that, you'll have TLB lookups, which could hurt performance.
+ */
+mmu_sect_map_t mem_map[] = {
+/* <phys addr> <virt addr> <size> <flags> */
+ {0x08200000, 0x00000000, 1, MMU_CACHE_NONE}, /* Mirror of SDRAM */
+ {0x00100000, 0x00100000, 1, MMU_CACHE_NONE}, /* Bootstrap ROM */
+ {0x00200000, 0x00200000, 1, MMU_CACHE_NONE}, /* Internal Regs */
+ {0x08000000, 0x08000000, 32, MMU_CACHE_WTHROUGH}, /* SDRAM */
+ {0x10000000, 0x10000000, 8, MMU_CACHE_NONE}, /* CS0 - Flash */
+ {0x12000000, 0x12000000, 1, MMU_CACHE_NONE}, /* CS1 - enet */
+ {0x13000000, 0x13000000, 1, MMU_CACHE_NONE}, /* CS2 - */
+ {0x14000000, 0x14000000, 1, MMU_CACHE_NONE}, /* CS3 - */
+ {0x15000000, 0x15000000, 1, MMU_CACHE_NONE}, /* CS4 - */
+ {0x16000000, 0x16000000, 1, MMU_CACHE_NONE}, /* CS5 - */
+ {0x50000000, 0x50000000, 1, MMU_CACHE_NONE}, /* ARM Test Regs */
+ {0x00000000, 0x00000000, 0, 0} /* The end */
+};
diff --git a/c/src/lib/libbsp/arm/csb336/times b/c/src/lib/libbsp/arm/csb336/times
new file mode 100644
index 0000000000..d44e942599
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/times
@@ -0,0 +1,189 @@
+#
+# Timing Test Suite Results for the Cogent CSB336 MC9328MXL BSP
+#
+#
+#
+
+Board: Cogent CSB336
+CPU: MC9328MXL - ARM920T
+Clock Speed: 200 MHz
+Memory Configuration: SDRAM, 32 bits wide
+
+Times Reported in: microseconds
+Timer Source: Timer 2
+
+All tests were compiled with VARIANT=DEBUG
+Both instruction and data caches are enabled.
+
+
+
+== ==================================================================== ===
+ 1 rtems_semaphore_create 16
+ 1 rtems_semaphore_delete 17
+ 1 rtems_semaphore_obtain: available 2
+ 1 rtems_semaphore_obtain: not available -- NO_WAIT 2
+ 1 rtems_semaphore_release: no waiting tasks 5
+
+ 2 rtems_semaphore_obtain: not available -- caller blocks 20
+
+ 3 rtems_semaphore_release: task readied -- preempts caller 16
+
+ 4 rtems_task_restart: blocked task -- preempts caller 48
+ 4 rtems_task_restart: ready task -- preempts caller 36
+ 4 rtems_semaphore_release: task readied -- returns to caller 9
+ 4 rtems_task_create 33
+ 4 rtems_task_start 12
+ 4 rtems_task_restart: suspended task -- returns to caller 14
+ 4 rtems_task_delete: suspended task 31
+ 4 rtems_task_restart: ready task -- returns to caller 14
+ 4 rtems_task_restart: blocked task -- returns to caller 19
+ 4 rtems_task_delete: blocked task 32
+
+ 5 rtems_task_suspend: calling task 14
+ 5 rtems_task_resume: task readied -- preempts caller 12
+
+ 6 rtems_task_restart: calling task 14
+ 6 rtems_task_suspend: returns to caller 6
+ 6 rtems_task_resume: task readied -- returns to caller 6
+ 6 rtems_task_delete: ready task 32
+
+ 7 rtems_task_restart: suspended task -- preempts caller 24
+
+ 8 rtems_task_set_priority: obtain current priority 4
+ 8 rtems_task_set_priority: returns to caller 8
+ 8 rtems_task_mode: obtain current mode 2
+ 8 rtems_task_mode: no reschedule 2
+ 8 rtems_task_mode: reschedule -- returns to caller 4
+ 8 rtems_task_mode: reschedule -- preempts caller 19
+ 8 rtems_task_set_note 4
+ 8 rtems_task_get_note 4
+ 8 rtems_clock_set 9
+ 8 rtems_clock_get 0
+
+ 9 rtems_message_queue_create 54
+ 9 rtems_message_queue_send: no waiting tasks 8
+ 9 rtems_message_queue_urgent: no waiting tasks 8
+ 9 rtems_message_queue_receive: available 7
+ 9 rtems_message_queue_flush: no messages flushed 4
+ 9 rtems_message_queue_flush: messages flushed 5
+ 9 rtems_message_queue_delete 21
+
+10 rtems_message_queue_receive: not available -- NO_WAIT 4
+10 rtems_message_queue_receive: not available -- caller blocks 20
+
+11 rtems_message_queue_send: task readied -- preempts caller 18
+
+12 rtems_message_queue_send: task readied -- returns to caller 11
+
+13 rtems_message_queue_urgent: task readied -- preempts caller 19
+
+14 rtems_message_queue_urgent: task readied -- returns to caller 11
+
+15 rtems_event_receive: obtain current events 0
+15 rtems_event_receive: not available -- NO_WAIT 3
+15 rtems_event_receive: not available -- caller blocks 17
+15 rtems_event_send: no task readied 3
+15 rtems_event_receive: available 5
+15 rtems_event_send: task readied -- returns to caller 10
+
+16 rtems_event_send: task readied -- preempts caller 16
+
+17 rtems_task_set_priority: preempts caller 19
+
+18 rtems_task_delete: calling task 41
+
+19 rtems_signal_catch 6
+19 rtems_signal_send: returns to caller 15
+19 rtems_signal_send: signal to self 25
+19 exit ASR overhead: returns to calling task 11
+19 exit ASR overhead: returns to preempting task 12
+
+20 rtems_partition_create 22
+20 rtems_region_create 30
+20 rtems_partition_get_buffer: available 10
+20 rtems_partition_get_buffer: not available 4
+20 rtems_partition_return_buffer 9
+20 rtems_partition_delete 10
+20 rtems_region_get_segment: available 15
+20 rtems_region_get_segment: not available -- NO_WAIT 16
+20 rtems_region_return_segment: no waiting tasks 13
+20 rtems_region_get_segment: not available -- caller blocks 47
+20 rtems_region_return_segment: task readied -- preempts caller 45
+20 rtems_region_return_segment: task readied -- returns to caller 25
+20 rtems_region_delete 23
+20 rtems_io_initialize 1
+20 rtems_io_open 0
+20 rtems_io_close 0
+20 rtems_io_read 0
+20 rtems_io_write 0
+20 rtems_io_control 0
+
+21 rtems_task_ident 39
+21 rtems_message_queue_ident 38
+21 rtems_semaphore_ident 43
+21 rtems_partition_ident 38
+21 rtems_region_ident 38
+21 rtems_port_ident 37
+21 rtems_timer_ident 38
+21 rtems_rate_monotonic_ident 38
+
+22 rtems_message_queue_broadcast: task readied -- returns to caller 27
+22 rtems_message_queue_broadcast: no waiting tasks 6
+22 rtems_message_queue_broadcast: task readied -- preempts caller 22
+
+23 rtems_timer_create 4
+23 rtems_timer_fire_after: inactive 7
+23 rtems_timer_fire_after: active 7
+23 rtems_timer_cancel: active 4
+23 rtems_timer_cancel: inactive 3
+23 rtems_timer_reset: inactive 6
+23 rtems_timer_reset: active 7
+23 rtems_timer_fire_when: inactive 9
+23 rtems_timer_fire_when: active 9
+23 rtems_timer_delete: active 5
+23 rtems_timer_delete: inactive 4
+23 rtems_task_wake_when 21
+
+24 rtems_task_wake_after: yield -- returns to caller 2
+24 rtems_task_wake_after: yields -- preempts caller 12
+
+25 rtems_clock_tick 13
+
+26 _ISR_Disable 3
+26 _ISR_Flash 1
+26 _ISR_Enable 0
+26 _Thread_Disable_dispatch 1
+26 _Thread_Enable_dispatch 3
+26 _Thread_Set_state 6
+26 _Thread_Disptach (NO FP) 13
+26 context switch: no floating point contexts 10
+26 context switch: self 1
+26 context switch: to another task 2
+26 fp context switch: restore 1st FP task - NA
+26 fp context switch: save idle, restore initialized - NA
+26 fp context switch: save idle, restore idle - NA
+26 fp context switch: save initialized, restore initialized - NA
+26 _Thread_Resume 9
+26 _Thread_Unblock 8
+26 _Thread_Ready 5
+26 _Thread_Get 1
+26 _Semaphore_Get 0
+26 _Thread_Get: invalid id 0
+
+27 interrupt entry overhead: returns to interrupted task 0
+27 interrupt exit overhead: returns to interrupted task 1
+27 interrupt entry overhead: returns to nested interrupt 0
+27 interrupt exit overhead: returns to nested interrupt 0
+
+28 rtems_port_create 13
+28 rtems_port_external_to_internal 3
+28 rtems_port_internal_to_external 3
+28 rtems_port_delete 11
+
+29 rtems_rate_monotonic_create 13
+29 rtems_rate_monotonic_period: initiate period -- returns to caller 24
+29 rtems_rate_monotonic_period: obtain status 5
+29 rtems_rate_monotonic_cancel 15
+29 rtems_rate_monotonic_delete: inactive 12
+29 rtems_rate_monotonic_delete: active 7
+29 rtems_rate_monotonic_period: conclude periods -- caller blocks 13