doc: Add new documentation section for Epiphany architecture

3 files changed, 83 insertions, 0 deletions

diff --git a/doc/cpu_supplement/Makefile.am b/doc/cpu_supplement/Makefile.am
index 300ff786cc..06ebf48970 100644
--- a/doc/cpu_supplement/Makefile.am
+++ b/doc/cpu_supplement/Makefile.am
@@ -15,6 +15,7 @@ GENERATED_FILES += general.texi
 GENERATED_FILES += arm.texi
 GENERATED_FILES += avr.texi
 GENERATED_FILES += bfin.texi
+GENERATED_FILES += epiphany.texi
 GENERATED_FILES += h8300.texi
 GENERATED_FILES += i386.texi
 GENERATED_FILES += lm32.texi
@@ -62,6 +63,11 @@ bfin.texi: bfin.t
 	    -u "Top" \
 	    -n "" < $< > $@
 
+epiphany.texi: epiphany.t
+	$(BMENU2) -p "" \
+	    -u "Top" \
+	    -n "" < $< > $@
+
 h8300.texi: h8300.t
 	$(BMENU2) -p "" \
 	    -u "Top" \
diff --git a/doc/cpu_supplement/cpu_supplement.texi b/doc/cpu_supplement/cpu_supplement.texi
index 5c484d031f..105a54e9a4 100644
--- a/doc/cpu_supplement/cpu_supplement.texi
+++ b/doc/cpu_supplement/cpu_supplement.texi
@@ -65,6 +65,7 @@
 * ARM Specific Information::
 * Atmel AVR Specific Information::
 * Blackfin Specific Information::
+* Epiphany Specific Information::
 * Renesas H8/300 Specific Information::
 * Intel/AMD x86 Specific Information::
 * Lattice Mico32 Specific Information::
@@ -89,6 +90,7 @@
 @include arm.texi
 @include avr.texi
 @include bfin.texi
+@include epiphany.texi
 @include h8300.texi
 @include i386.texi
 @include lm32.texi
diff --git a/doc/cpu_supplement/epiphany.t b/doc/cpu_supplement/epiphany.t
new file mode 100644
index 0000000000..a0976cf3b6
--- /dev/null
+++ b/doc/cpu_supplement/epiphany.t
@@ -0,0 +1,75 @@
+@c
+@c  Copyright (c) 2015 University of York.
+@c  Hesham ALMatary <hmka501@york.ac.uk>
+
+@ifinfo
+@end ifinfo
+@chapter Epiphany Specific Information
+
+This chapter discusses the
+@uref{http://adapteva.com/docs/epiphany_sdk_ref.pdf, Epiphany Architecture}
+dependencies in this port of RTEMS. Epiphany is a chip that can come with 16 and
+64 cores, each of which can run RTEMS separately or they can work together to 
+run a SMP RTEMS application.
+
+@subheading Architecture Documents
+
+For information on the Epiphany architecture refer to the
+@uref{http://adapteva.com/docs/epiphany_arch_ref.pdf,Epiphany Architecture Reference}.
+
+@section Calling Conventions
+
+Please refer to the
+@uref{http://adapteva.com/docs/epiphany_sdk_ref.pdf, Epiphany SDK}
+Appendix A: Application Binary Interface
+
+@subsection Floating Point Unit
+
+A floating point unit is currently not supported.
+
+@section Memory Model
+
+A flat 32-bit memory model is supported, no caches. Each core has its own 32 KiB
+strictly ordered local memory along with an access to a shared 32 MiB external
+DRAM.
+
+@section Interrupt Processing
+
+Every Epiphany core has 10 exception types:
+
+@itemize @bullet
+
+@item Reset
+@item Software Exception
+@item Data Page Fault
+@item Timer 0
+@item Timer 1
+@item Message Interrupt
+@item DMA0 Interrupt
+@item DMA1 Interrupt
+@item WANT Interrupt
+@item User Interrupt
+
+@end itemize
+
+@subsection Interrupt Levels
+
+There are only two levels: interrupts enabled and interrupts disabled.
+
+@subsection Interrupt Stack
+
+The Epiphany RTEMS port uses a dedicated software interrupt stack.
+The stack for interrupts is allocated during interrupt driver initialization.
+When an  interrupt is entered, the _ISR_Handler routine is responsible for
+switching from the interrupted task stack to RTEMS software interrupt stack.
+
+@section Default Fatal Error Processing
+
+The default fatal error handler for this architecture performs the
+following actions:
+
+@itemize @bullet
+@item disables operating system supported interrupts (IRQ),
+@item places the error code in @code{r0}, and
+@item executes an infinite loop to simulate a halt processor instruction.
+@end itemize