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authorJoel Sherrill <joel.sherrill@OARcorp.com>2003-02-14 19:40:49 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2003-02-14 19:40:49 +0000
commit04040112b64421ac0d1bc751800469271d46e1ce (patch)
tree1f3dce85a0e6edb716257b350cdb271913f2efa4
parent2003-02-14 Joel Sherrill <joel@OARcorp.com> (diff)
downloadrtems-04040112b64421ac0d1bc751800469271d46e1ce.tar.bz2
2003-02-14 Joel Sherrill <joel@OARcorp.com>
AMD a29k declared obsolete. * cpu/Makefile.am: Removed reference. * cpu/a29k/.cvsignore, cpu/a29k/ChangeLog, cpu/a29k/Makefile.am, cpu/a29k/amd.ah, cpu/a29k/asm.h, cpu/a29k/configure.ac, cpu/a29k/cpu.c, cpu/a29k/cpu_asm.S, cpu/a29k/pswmacro.ah, cpu/a29k/register.ah, cpu/a29k/sig.S, cpu/a29k/rtems/.cvsignore, cpu/a29k/rtems/score/.cvsignore, cpu/a29k/rtems/score/a29k.h, cpu/a29k/rtems/score/cpu.h, cpu/a29k/rtems/score/cpu_asm.h, cpu/a29k/rtems/score/types.h: Removed.
Diffstat
-rw-r--r--cpukit/score/ChangeLog12
-rw-r--r--cpukit/score/cpu/Makefile.am2
-rw-r--r--cpukit/score/cpu/a29k/.cvsignore14
-rw-r--r--cpukit/score/cpu/a29k/ChangeLog162
-rw-r--r--cpukit/score/cpu/a29k/Makefile.am51
-rw-r--r--cpukit/score/cpu/a29k/amd.ah534
-rw-r--r--cpukit/score/cpu/a29k/asm.h101
-rw-r--r--cpukit/score/cpu/a29k/configure.ac30
-rw-r--r--cpukit/score/cpu/a29k/cpu.c286
-rw-r--r--cpukit/score/cpu/a29k/cpu_asm.S522
-rw-r--r--cpukit/score/cpu/a29k/pswmacro.ah442
-rw-r--r--cpukit/score/cpu/a29k/register.ah217
-rw-r--r--cpukit/score/cpu/a29k/rtems/.cvsignore2
-rw-r--r--cpukit/score/cpu/a29k/rtems/score/.cvsignore2
-rw-r--r--cpukit/score/cpu/a29k/rtems/score/a29k.h78
-rw-r--r--cpukit/score/cpu/a29k/rtems/score/cpu.h1008
-rw-r--r--cpukit/score/cpu/a29k/rtems/score/cpu_asm.h71
-rw-r--r--cpukit/score/cpu/a29k/rtems/score/types.h56
-rw-r--r--cpukit/score/cpu/a29k/sig.S213
19 files changed, 13 insertions, 3790 deletions
diff --git a/cpukit/score/ChangeLog b/cpukit/score/ChangeLog
index e5b472fb02..59d434ca44 100644
--- a/cpukit/score/ChangeLog
+++ b/cpukit/score/ChangeLog
@@ -1,3 +1,15 @@
+2003-02-14 Joel Sherrill <joel@OARcorp.com>
+
+ AMD a29k declared obsolete.
+ * cpu/Makefile.am: Removed reference.
+ * cpu/a29k/.cvsignore, cpu/a29k/ChangeLog, cpu/a29k/Makefile.am,
+ cpu/a29k/amd.ah, cpu/a29k/asm.h, cpu/a29k/configure.ac,
+ cpu/a29k/cpu.c, cpu/a29k/cpu_asm.S, cpu/a29k/pswmacro.ah,
+ cpu/a29k/register.ah, cpu/a29k/sig.S, cpu/a29k/rtems/.cvsignore,
+ cpu/a29k/rtems/score/.cvsignore, cpu/a29k/rtems/score/a29k.h,
+ cpu/a29k/rtems/score/cpu.h, cpu/a29k/rtems/score/cpu_asm.h,
+ cpu/a29k/rtems/score/types.h: Removed.
+
2003-01-10 Joel Sherrill <joel@OARcorp.com>
* src/objectmp.c: Corrected use of name parameter to reflect that it
diff --git a/cpukit/score/cpu/Makefile.am b/cpukit/score/cpu/Makefile.am
index 3e84557494..f20fabb5de 100644
--- a/cpukit/score/cpu/Makefile.am
+++ b/cpukit/score/cpu/Makefile.am
@@ -7,7 +7,7 @@ SUBDIRS = $(RTEMS_CPU)
## FIXME: this does not work
## DIST_SUBDIRS = \
-## a29k hppa1.1 i386 i960 m68k mips64orion no_cpu powerpc sh sparc unix
+## arm hppa1.1 i386 i960 m68k mips64orion no_cpu powerpc sh sparc unix
include $(top_srcdir)/automake/subdirs.am
include $(top_srcdir)/automake/local.am
diff --git a/cpukit/score/cpu/a29k/.cvsignore b/cpukit/score/cpu/a29k/.cvsignore
deleted file mode 100644
index bfdfd995be..0000000000
--- a/cpukit/score/cpu/a29k/.cvsignore
+++ /dev/null
@@ -1,14 +0,0 @@
-aclocal.m4
-autom4te*.cache
-config.cache
-config.guess
-config.log
-config.status
-config.sub
-configure
-depcomp
-install-sh
-Makefile
-Makefile.in
-missing
-mkinstalldirs
diff --git a/cpukit/score/cpu/a29k/ChangeLog b/cpukit/score/cpu/a29k/ChangeLog
deleted file mode 100644
index 8663872d8d..0000000000
--- a/cpukit/score/cpu/a29k/ChangeLog
+++ /dev/null
@@ -1,162 +0,0 @@
-2003-02-11 Joel Sherrill <joel@OARcorp.com>
-
- * cpu_asm.c: Rework logic that decides when to call
- _Thread_Dispatch. Analysis by Sergei Organov <osv@javad.ru>
- determined that _ISR_Signals_to_thread_executing was not being
- honored and/or cleared properly.
-
-2002-12-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Require autoconf-2.57 + automake-1.7.2.
- * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
-
-2002-11-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Fix package name.
-
-2002-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
-
-2002-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * .cvsignore: Reformat.
- Add autom4te*cache.
- Remove autom4te.cache.
-
-2002-07-26 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Build libscorecpu.a instead of rtems-cpu.rel.
-
-2002-07-22 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Use .$(OBJEXT) instead of .o.
-
-2002-07-22 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Use . instead of .o.
-
-2002-07-05 Joel Sherrill <joel@OARcorp.com>
-
- * rtems/score/cpu.h: Filled in something that was marked XXX.
-
-2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: RTEMS_TOP(../../../..).
-
-2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * rtems.c: Remove.
- * Makefile.am: Reflect changes above.
-
-2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Remove RTEMS_PROJECT_ROOT.
-
-2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Add RTEMS_PROG_CCAS
-
-2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
- Add AC_PROG_RANLIB.
-
-2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
- Use ../../../aclocal.
-
-2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * asm.h: Use cpuopts.h instead of targopts.h.
-
-2001-04-03 Joel Sherrill <joel@OARcorp.com>
-
- * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
- * rtems/score/a29ktypes.h: Removed.
- * rtems/score/types.h: New file via CVS magic.
- * Makefile.am, rtems/score/cpu.h: Account for name change.
-
-2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac:
- AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
- AM_INIT_AUTOMAKE([no-define foreign 1.6]).
- * Makefile.am: Remove AUTOMAKE_OPTIONS.
-
-2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * rtems/Makefile.am: Removed.
- * rtems/score/Makefile.am: Removed.
- * configure.ac: Reflect changes above.
- * Makefile.am: Reflect changes above.
-
-2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Add multilib support.
-
-2001-11-28 Joel Sherrill <joel@OARcorp.com>,
-
- This was tracked as PR91.
- * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
- is used to specify if the port uses the standard macro for this (FALSE).
- A TRUE setting indicates the port provides its own implementation.
-
-2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * .cvsignore: Add autom4te.cache for autoconf > 2.52.
- * configure.in: Remove.
- * configure.ac: New file, generated from configure.in by autoupdate.
-
-2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
- * Makefile.am: Use 'PREINSTALL_FILES ='.
-
-2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am, rtems/score/Makefile.am:
- Apply include_*HEADERS instead of H_FILES.
-
-2001-01-03 Joel Sherrill <joel@OARcorp.com>
-
- * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
-
-2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
-
-2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
-
-2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
- Switch to GNU canonicalization.
-
-2000-09-25 Joel Sherrill <joel@OARcorp.com>
-
- * rtems/score/a29k.h, rtems/score/cpu.h: Switched to using
- cpuopts.h not targopts.h to reduce dependency on BSP.
-
-2000-09-22 Joel Sherrill <joel@OARcorp.com>
-
- * amd.ah, cpu.c, cpu_asm.S, register.ah, sig.S, rtems/score/cpu.h:
- Updated and fixed minor things. Commented out offensive assembly
- and made applications link.
-
-2000-09-22 Joel Sherrill <joel@OARcorp.com>
-
- * Makefile.am, cpu_asm.S, psmacro.ah, rtems/score/cpu.h:
- First attempt to compile with GNU tools. Minor modifications
- to compile enough to get to assembler errors.
-
-2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Include compile.am, remove duplicate includes.
-
-2000-08-10 Joel Sherrill <joel@OARcorp.com>
-
- * ChangeLog: New file.
diff --git a/cpukit/score/cpu/a29k/Makefile.am b/cpukit/score/cpu/a29k/Makefile.am
deleted file mode 100644
index 32ed3d2a90..0000000000
--- a/cpukit/score/cpu/a29k/Makefile.am
+++ /dev/null
@@ -1,51 +0,0 @@
-##
-## $Id$
-##
-
-ACLOCAL_AMFLAGS = -I ../../../aclocal
-
-include $(top_srcdir)/../../../automake/multilib.am
-include $(top_srcdir)/../../../automake/compile.am
-include $(top_srcdir)/../../../automake/lib.am
-
-$(PROJECT_INCLUDE)/%.h: %.h
- $(INSTALL_DATA) $< $@
-
-$(PROJECT_INCLUDE):
- $(mkinstalldirs) $@
-
-$(PROJECT_INCLUDE)/rtems:
- $(mkinstalldirs) $@
-
-$(PROJECT_INCLUDE)/rtems/score:
- $(mkinstalldirs) $@
-
-include_HEADERS = amd.ah asm.h pswmacro.ah register.ah
-PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%)
-
-include_rtems_scoredir = $(includedir)/rtems/score
-include_rtems_score_HEADERS = \
- rtems/score/a29k.h \
- rtems/score/types.h \
- rtems/score/cpu.h \
- rtems/score/cpu_asm.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \
- $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h)
-
-C_FILES = cpu.c
-OBJS = $(C_FILES:%.c=$(ARCH)/%.$(OBJEXT))
-
-S_FILES = cpu_asm.S sig.S
-OBJS += $(S_FILES:%.S=$(ARCH)/%.$(OBJEXT))
-
-LIB = $(ARCH)/libscorecpu.a
-
-$(LIB): $(OBJS)
- $(make-library)
-
-all-local: $(ARCH) $(PREINSTALL_FILES) $(LIB) \
- $(TMPINSTALL_FILES)
-
-EXTRA_DIST = cpu.c cpu_asm.S sig.S
-
-include $(top_srcdir)/../../../automake/local.am
diff --git a/cpukit/score/cpu/a29k/amd.ah b/cpukit/score/cpu/a29k/amd.ah
deleted file mode 100644
index 84a749edea..0000000000
--- a/cpukit/score/cpu/a29k/amd.ah
+++ /dev/null
@@ -1,534 +0,0 @@
-#if 0
-
-; /* @(#)amd.ah 1.1 96/05/23 08:56:58, TEI */
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Initialization values for registers after RESET
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;
-: /* $Id$ */
-;* File information and includes.
-
-#endif
- .file "amd.ah"
- .ident "@(#)amd.ah 1.1 96/05/23 08:56:58, TEI"
-
-
-
-;
-;* AMD PROCESSOR SPECIFIC VALUES...
-;
-
-;
-;* Processor revision levels...
-;
-
-; PRL values: 31-28 27-24
-; Am29000 0 x
-; Am29005 1 x
-; Am29050 2 x
-; Am29035 3 x
-; Am29030 4 x
-; Am29200 5 x
-; Am29205 5 1x
-; Am29240 6 0
-; Manx 7 0
-; Cougar 8 0
-
-
- .equ AM29000_PRL, 0x00
-
- .equ AM29005_PRL, 0x10
-
- .equ AM29050_PRL, 0x20
-
- .equ AM29035_PRL, 0x30
-
- .equ AM29030_PRL, 0x40
-
- .equ AM29200_PRL, 0x50
-
- .equ AM29205_PRL, 0x58
-
- .equ AM29240_PRL, 0x60
-
- .equ AM29040_PRL, 0x70
-
- .equ MANX_PRL, 0x70
-
- .equ COUGAR_PRL, 0x80
-
-;
-;* data structures sizes.
-;
- .equ CFGINFO_SIZE, 16*4
-
- .equ PGMINFO_SIZE, 16*4
-
- .equ VARARGS_SPACE, 16*4
-
- .equ WINDOWSIZE, 0x80
-;
-;* Am29027 Mode registers
-;
-
- .equ Am29027Mode1, 0x0fc00820
-
- .equ Am29027Mode2, 0x00001375
-
-
-
-;* Processor Based Equates and Defines
-
- .equ SIG_SYNC, -1
-
- .equ ENABLE, (SM)
-
- .equ DISABLE, (ENABLE | DI | DA)
-
- .equ DISABLE_FZ, (FZ | ENABLE | DI | DA)
-
- .equ CLR_TRAP, (FZ | DA)
-
- .equ InitOPS, (TD | SM | (3<<IMShift) | DI | DA)
-
- .equ InitCPS, (TD | SM | (0<<IMShift) | DI | DA)
-
- .equ InitCPS1, (TD | SM | (0<<IMShift) | DI )
-
- .equ CPS_TMR, (SM | (0<<IMShift) | DI)
-
- .equ CPS_INT0, (TD | SM | (0<<IMShift))
-
- .equ CPS_TMRINT0, (SM | (0<<IMShift))
-
- .equ InitCFG, 0x0
-
- .equ InitRBP, (B0|B1|B2|B3|B4|B5)
-
- .equ TMC_VALUE, 0xFFFFFF
-
- .equ TMR_VALUE, (IE | TMC_VALUE)
-
-
-
-
-
-
-;* 29205 specific (internal) peripheral initialization constants.
-
-; Current Processor Status (CPS) Register.
-; Old Processor Status Register (OPS).
-
- .equ DA, 0x00001
- .equ DI, 0x00002
- .equ IMShift,0x2
- .equ SM, 0x00010
- .equ PI, 0x00020
- .equ PD, 0x00040
- .equ WM, 0x00080
- .equ RE, 0x00100
- .equ LK, 0x00200
- .equ FZ, 0x00400
- .equ TU, 0x00800
- .equ TP, 0x01000
- .equ TE, 0x02000
- .equ IP, 0x04000
- .equ CA, 0x08000
- .equ MM, 0x10000
- .equ TD, 0x20000
-
-; Configuration Register (CFG)
-
- .equ CD, 0x01
- .equ CP, 0x02
- .equ BO, 0x04
- .equ RV, 0x08
- .equ VF, 0x10
- .equ DW, 0x20
- .equ CO, 0x40
- .equ EE, 0x80
- .equ IDShift, 8
- .equ CFG_ID, 0x100
- .equ ILShift, 9
- .equ CFG_ILMask, 0x600
- .equ DDShift, 11
- .equ CFG_DD, 0x800
- .equ DLShift, 12
- .equ CFG_DLMask, 0x3000
- .equ PCEShift, 14
- .equ CFG_PCE, 0x4000
- .equ PMBShift, 16
- .equ D16, 0x8000
- .equ TBOShift, 23
- .equ PRLShift, 24
-
-; Channel Control Register (CHC)
-
- .equ CV, 0x1
- .equ NN, 0x2
- .equ TRShift, 2
- .equ TF, 0x400
- .equ PER, 0x800
- .equ LA, 0x1000
- .equ ST, 0x2000
- .equ ML, 0x4000
- .equ LS, 0x8000
- .equ CRShift, 16
- .equ CNTLShift, 24
- .equ CEShift, 31
- .equ WBERShift, 31
-
-; Register Bank Protect (RBP)
- .equ B0, 0x1
- .equ B1, 0x2
- .equ B2, 0x4
- .equ B3, 0x8
- .equ B4, 0x10
- .equ B5, 0x20
- .equ B6, 0x40
- .equ B7, 0x80
- .equ B8, 0x100
- .equ B9, 0x200
- .equ B10, 0x400
- .equ B11, 0x800
- .equ B12, 0x1000
- .equ B13, 0x2000
- .equ B14, 0x4000
- .equ B15, 0x8000
-
-; Timer Counter
-
- .equ TCVMask, 0xffffff
-
-; Timer Reload Register
-
- .equ IE, 0x1000000
- .equ IN, 0x2000000
- .equ OV, 0x4000000
- .equ TRVMAsk, 0xffffff
-
-; MMU Configuration
-
- .equ PSShift, 8
- .equ PS0Shift, 8
- .equ PS1Shift, 12
-
-; LRU Recommendation (LRU)
- .equ LRUMask, 0xff
-
-; Reason Vector (RSN)
- .equ RSNMask, 0xff
-
-; Region Mapping Address (RMA0 | RMA1)
- .equ PBAMask,0xffff
- .equ VBAShift, 16
-
-; Region Mapping Control (RMC0 | RMC1)
- .equ TIDMask, 0xff
- .equ RMC_UE, 0x100
- .equ RMC_UW, 0x200
- .equ RMC_UR, 0x400
- .equ RMC_SE, 0x800
- .equ RMC_SW, 0x1000
- .equ RMC_SR, 0x2000
- .equ RMC_VE, 0x4000
- .equ RMC_IO, 0x10000
- .equ RGSShift, 17
- .equ RMC_PGMShift, 22
-
-; Instruction breakpoint Control (IBC0 | IBC1)
- .equ BPIDMask, 0xff
- .equ BTE, 0x100
- .equ BRM, 0x200
- .equ IBC_BSY, 0x400
- .equ BEN, 0x800
- .equ BHO, 0x1000
-
-; Cache Data Register (CDR)
- .equ CDR_US, 0x1
- .equ P, 0x2
- .equ CDR_V, 0x4
- .equ IATAGShift, 20
-
-; Cache Interface Register (CIR)
- .equ CPTRShift, 2
- .equ CIR_RW, 0x1000000
- .equ FSELShift, 28
-
-; Indirect Pointer A, B, C (IPA, IPB, IPC)
- .equ IPShift, 2
-
-; ALU Status (ALU)
- .equ FCMask, 0x1F
- .equ BPShift, 5
- .equ C, 0x80
- .equ Z, 0x100
- .equ N, 0x200
- .equ ALU_V, 0x400
- .equ DF, 0x800
-
-; Byte Pointer
- .equ BPMask, 0x3
-
-; Load/Store Count Remaining (CR)
- .equ CRMask, 0xff
-
-; Floating Point Environment (FPE)
- .equ NM, 0x1
- .equ RM, 0x2
- .equ VM, 0x4
- .equ UM, 0x8
- .equ XM, 0x10
- .equ DM, 0x20
- .equ FRMShift, 6
- .equ FF, 0x100
- .equ ACFShift, 9
-
-; Integer Environment (INTE)
- .equ MO, 0x1
- .equ DO, 0x2
-
-; Floating Point Status (FPS)
- .equ NS, 0x1
- .equ RS, 0x2
- .equ VS, 0x4
- .equ FPS_US, 0x8
- .equ XS, 0x10
- .equ DS, 0x20
- .equ NT, 0x100
- .equ RT, 0x200
- .equ VT, 0x400
- .equ UT, 0x800
- .equ XT, 0x1000
- .equ DT, 0x2000
-
-; Exception Opcode (EXOP)
- .equ IOPMask, 0xff
-
-; TLB Entry Word 0
-; .equ TIDMask, 0xff already defined above
- .equ TLB_UE, 0x100
- .equ TLB_UW, 0x200
- .equ TLB_UR, 0x400
- .equ TLB_SE, 0x800
- .equ TLB_SW, 0x1000
- .equ TLB_SR, 0x2000
- .equ TLB_VE, 0x4000
- .equ VTAGShift, 15
-
-; TLB Entry Word 1
- .equ TLB_IO, 0x1
- .equ U, 0x2
- .equ TLB_PGMShift, 6
- .equ RPNShift, 10
-
-; Am29200 ROM Control bits.
- .equ RMCT_DW0Shift, 29
- .equ RMCT_DW1Shift, 21
- .equ RMCT_DW2Shift, 13
- .equ RMCT_DW3Shift, 5
-
-; Am29200 DRAM Control bits.
- .equ DW3, (1<<18)
- .equ DW2, (1<<22)
- .equ DW1, (1<<26)
- .equ DW0, (1<<30)
-
- ; Internal peripheral address assignments.
- .equ RMCT, 0x80000000
- .equ RMCF, 0x80000004
- .equ DRCT, 0x80000008
- .equ DRCF, 0x8000000C
- .equ DRM0, 0x80000010
- .equ DRM1, 0x80000014
- .equ DRM2, 0x80000018
- .equ DRM3, 0x8000001C
- .equ PIACT0, 0x80000020
- .equ PIACT1, 0x80000020
- .equ ICT, 0x80000028
- .equ DMCT0, 0x80000030
- .equ DMAD0, 0x80000034
- .ifdef revA
- .equ TAD0, 0x80000036
- .equ TCN0, 0x8000003A
- .else
- .equ TAD0, 0x80000070 ; default
- .equ TCN0, 0x8000003C ; default
- .endif
- .equ DMCN0, 0x80000038
- .equ DMCT1, 0x80000040
- .equ DMAD1, 0x80000044
- .equ DMCN1, 0x80000048
- .equ SPCT, 0x80000080
- .equ SPST, 0x80000084
- .equ SPTH, 0x80000088
- .equ SPRB, 0x8000008C
- .equ BAUD, 0x80000090
- .equ PPCT, 0x800000C0
- .equ PPST, 0x800000C1
- .equ PPDT, 0x800000C4
- .equ POCT, 0x800000D0
- .equ PIN, 0x800000D4
- .equ POUT, 0x800000D8
- .equ POEN, 0x800000DC
- .equ VCT, 0x800000E0
- .equ TOP, 0x800000E4
- .equ SIDE, 0x800000E8
- .equ VDT, 0x800000EC
-
- ; Interrupt Controller Register bits.
- .equ TXDI, (1<<5)
- .equ RXDI, (1<<6)
- .equ RXSI, (1<<7)
- .equ PPI, (1<<11)
- .equ DMA1I, (1<<13)
- .equ DMA0I, (1<<14)
- .equ IOPIMask, (0xFF<<16)
- .equ VDI, (1<<27)
- .equ ICT200_I, (TXDI|RXDI|RXSI|PPI|DMA1I|DMA0I|IOPIMask|VDI)
- .equ ICT205_I, (TXDI|RXDI|RXSI|PPI|DMA1I|DMA0I|IOPIMask|VDI)
-
- ; Serial port Initialization bits
- .equ NO_PARITY, 0
-
-
- ; SPST bits
- .equ THREShift, 22
-
-;* REGISTER Addresses
-
- .equ ROMCntlRegAddr, 0x80000000
-
- .equ ROMCfgRegAddr, 0x80000004
-
- .equ DRAMCntlRegAddr, 0x80000008
-
- .equ DRAMCfgRegAddr, 0x8000000C
-
- .equ DRAMMap0RegAddr, 0x80000010
-
- .equ DRAMMap1RegAddr, 0x80000014
-
- .equ DRAMMap2RegAddr, 0x80000018
-
- .equ DRAMMap3RegAddr, 0x8000001C
-
- .equ PIACntl0RegAddr, 0x80000020
-
- .equ PIACntl1RegAddr, 0x80000024
-
- .equ INTRCntlRegAddr, 0x80000028
-
- .equ DMACntl0RegAddr, 0x80000030
-
- .equ DMACntl1RegAddr, 0x80000040
-
- .equ SERPortCntlRegAddr, 0x80000080
-
- .equ SERPortStatRegAddr, 0x80000084
-
- .equ SERPortTHLDRegAddr, 0x80000088
-
- .equ SERPortRbufRegAddr, 0x8000008C
-
- .equ SERPortBaudRegAddr, 0x80000090
-
- .equ PARPortCntlRegAddr, 0x800000C0
-
- .equ PIOCntlRegAddr, 0x800000D0
-
- .equ PIOInpRegAddr, 0x800000D4
-
- .equ PIOOutRegAddr, 0x800000D8
-
- .equ PIOOutEnaRegAddr, 0x800000DC
-
- .equ VCTCntlRegAddr, 0x800000E0
-
-;
-;* Control constants
-;
-
-;* AM29030 Timer related constants.
-
- .equ TMR_IE, 0x01000000
-
- .equ TMR_IN, 0x02000000
-
- .equ TMR_OV, 0x04000000
-
- .equ TMC_INITCNT, 1613
-
-;
-;* System initialization values.
-;
-
- .equ __os_version, 0x0001 ;
-
- .equ STACKSize, 0x8000 ;
-
- .equ PGMExecMode, 0x0000 ;
-
- .equ TSTCK_OFST, 28 * 4
-
- .equ CSTCK_OFST, 29 * 4
-
- .equ TMSTCK_OFST, 30 * 4
-
- .equ CMSTCK_OFST, 31 * 4
-
- .equ CTXSW_OK, 0xA55A ; ctx switch ok
-
- .set NV_STARTOFST, 0x20 ; 32 bytes
-
- .set NV_BAUDOFST, 0x00 ; 00 bytes
-
- .set reg_cir, 29
-
- .set reg_cdr, 30
-
- .equ MSG_BUFSIZE, 0x1000 ; serial buffer size
-
- .equ ILLOPTRAP, 0
-
- .equ UATRAP, 1
-
- .equ PVTRAP, 5
-
- .equ UITLBMISSTRAP, 8
-
- .equ UDTLBMISSTRAP, 9
-
- .equ TIMERTRAP, 14
-
- .equ TRACETRAP, 15
-
- .equ XLINXTRAP, 16
-
- .equ SERIALTRAP, 17
-
- .equ SLOWTMRTRAP, 18
-
- .equ PORTTRAP, 19
-
- .equ SVSCTRAP, 80
-
- .equ SVSCTRAP1, 81
-
- .equ V_CACHETRAP, 66 ;
-
- .equ V_SETSERVICE, 67 ;
-
- .equ INIT_TIMER, 100
-
- .equ DISABLE_TIMER, 101
-
- .equ GET_TIMER, 102
-
- .equ CLEAR_TIMER, 103
-
- .equ V_SPILL, 64
-
- .equ V_FILL, 65
-
- .equ SIGDFL, 105
diff --git a/cpukit/score/cpu/a29k/asm.h b/cpukit/score/cpu/a29k/asm.h
deleted file mode 100644
index 51e77ec194..0000000000
--- a/cpukit/score/cpu/a29k/asm.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* asm.h
- *
- * This include file attempts to address the problems
- * caused by incompatible flavors of assemblers and
- * toolsets. It primarily addresses variations in the
- * use of leading underscores on symbols and the requirement
- * that register names be preceded by a %.
- *
- *
- * NOTE: The spacing in the use of these macros
- * is critical to them working as advertised.
- *
- * !!! THIS FILE DOES NOT APPEAR TO HAVE BEEN USED IN THE 29K PORT !!!
- *
- * COPYRIGHT:
- *
- * This file is based on similar code found in newlib available
- * from ftp.cygnus.com. The file which was used had no copyright
- * notice. This file is freely distributable as long as the source
- * of the file is noted. This file is:
- *
- * COPYRIGHT (c) 1989-1997
- * On-Line Applications Research Corporation (OAR).
- *
- * $Id$
- */
-
-#ifndef __A29K_ASM_h
-#define __A29K_ASM_h
-
-/*
- * Indicate we are in an assembly file and get the basic CPU definitions.
- */
-
-#ifndef ASM
-#define ASM
-#endif
-#include <rtems/score/cpuopts.h>
-#include <rtems/score/asm.h>
-
-/*
- * Recent versions of GNU cpp define variables which indicate the
- * need for underscores and percents. If not using GNU cpp or
- * the version does not support this, then you will obviously
- * have to define these as appropriate.
- */
-
-#ifndef __USER_LABEL_PREFIX__
-#define __USER_LABEL_PREFIX__ _
-#endif
-
-#ifndef __REGISTER_PREFIX__
-#define __REGISTER_PREFIX__
-#endif
-
-/* ANSI concatenation macros. */
-
-#define CONCAT1(a, b) CONCAT2(a, b)
-#define CONCAT2(a, b) a ## b
-
-/* Use the right prefix for global labels. */
-
-#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
-
-/* Use the right prefix for registers. */
-
-#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
-
-/*
- * define macros for all of the registers on this CPU
- *
- * EXAMPLE: #define d0 REG (d0)
- */
-
-/*
- * Define macros to handle section beginning and ends.
- */
-
-
-#define BEGIN_CODE_DCL .text
-#define END_CODE_DCL
-#define BEGIN_DATA_DCL .data
-#define END_DATA_DCL
-#define BEGIN_CODE .text
-#define END_CODE
-#define BEGIN_DATA
-#define END_DATA
-#define BEGIN_BSS
-#define END_BSS
-#define END
-
-/*
- * Following must be tailor for a particular flavor of the C compiler.
- * They may need to put underscores in front of the symbols.
- */
-
-#define PUBLIC(sym) .globl SYM (sym)
-#define EXTERN(sym) .globl SYM (sym)
-
-#endif
-/* end of include file */
diff --git a/cpukit/score/cpu/a29k/configure.ac b/cpukit/score/cpu/a29k/configure.ac
deleted file mode 100644
index 2ba4073b41..0000000000
--- a/cpukit/score/cpu/a29k/configure.ac
+++ /dev/null
@@ -1,30 +0,0 @@
-## Process this file with autoconf to produce a configure script.
-##
-## $Id$
-
-AC_PREREQ(2.57)
-AC_INIT([rtems-cpukit-score-cpu-a29k],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com])
-AC_CONFIG_SRCDIR([cpu_asm.S])
-RTEMS_TOP(../../../..)
-AC_CONFIG_AUX_DIR(../../../..)
-
-RTEMS_CANONICAL_TARGET_CPU
-
-AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.7.2])
-AM_MAINTAINER_MODE
-
-RTEMS_ENV_RTEMSCPU
-
-RTEMS_CHECK_CPU
-RTEMS_CANONICAL_HOST
-
-RTEMS_PROG_CC_FOR_TARGET
-RTEMS_PROG_CCAS
-RTEMS_CANONICALIZE_TOOLS
-AC_PROG_RANLIB
-
-RTEMS_CHECK_NEWLIB
-
-# Explicitly list all Makefiles here
-AC_CONFIG_FILES([Makefile])
-AC_OUTPUT
diff --git a/cpukit/score/cpu/a29k/cpu.c b/cpukit/score/cpu/a29k/cpu.c
deleted file mode 100644
index d522c07538..0000000000
--- a/cpukit/score/cpu/a29k/cpu.c
+++ /dev/null
@@ -1,286 +0,0 @@
-/*
- * AMD 29K CPU Dependent Source
- *
- * Author: Craig Lebakken <craigl@transition.com>
- *
- * COPYRIGHT (c) 1996 by Transition Networks Inc.
- *
- * To anyone who acknowledges that this file is provided "AS IS"
- * without any express or implied warranty:
- * permission to use, copy, modify, and distribute this file
- * for any purpose is hereby granted without fee, provided that
- * the above copyright notice and this notice appears in all
- * copies, and that the name of Transition Networks not be used in
- * advertising or publicity pertaining to distribution of the
- * software without specific, written prior permission.
- * Transition Networks makes no representations about the suitability
- * of this software for any purpose.
- *
- * Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
- *
- * COPYRIGHT (c) 1989-1999.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-#ifndef lint
-static char _sccsid[] = "@(#)cpu.c 10/21/96 1.8\n";
-#endif
-
-#include <rtems/system.h>
-#include <rtems/score/isr.h>
-#include <rtems/score/wkspace.h>
-#include <rtems/score/thread.h>
-#include <stdio.h>
-#include <stdlib.h>
-
-void a29k_ISR_Handler(unsigned32 vector);
-
-/* _CPU_Initialize
- *
- * This routine performs processor dependent initialization.
- *
- * INPUT PARAMETERS:
- * cpu_table - CPU table to initialize
- * thread_dispatch - address of disptaching routine
- */
-
-
-void _CPU_Initialize(
- rtems_cpu_table *cpu_table,
- void (*thread_dispatch)() /* ignored on this CPU */
-)
-{
- unsigned int i;
- /*
- * The thread_dispatch argument is the address of the entry point
- * for the routine called at the end of an ISR once it has been
- * decided a context switch is necessary. On some compilation
- * systems it is difficult to call a high-level language routine
- * from assembly. This allows us to trick these systems.
- *
- * If you encounter this problem save the entry point in a CPU
- * dependent variable.
- */
-
- _CPU_Thread_dispatch_pointer = thread_dispatch;
-
- /*
- * If there is not an easy way to initialize the FP context
- * during Context_Initialize, then it is usually easier to
- * save an "uninitialized" FP context here and copy it to
- * the task's during Context_Initialize.
- */
-
- /* FP context initialization support goes here */
-
- _CPU_Table = *cpu_table;
-
- for ( i = 0; i < ISR_NUMBER_OF_VECTORS; i++ )
- {
- _ISR_Vector_table[i] = (proc_ptr)NULL;
- }
-}
-
-/*PAGE
- *
- * _CPU_ISR_Get_level
- */
-
-unsigned32 _CPU_ISR_Get_level( void )
-{
- unsigned32 cps;
-
- /*
- * This routine returns the current interrupt level.
- */
- cps = a29k_getops();
- if (cps & (TD|DI))
- return 1;
- else
- return 0;
-}
-
-/*PAGE
- *
- * _CPU_ISR_install_raw_handler
- */
-
-extern void intr14( void );
-extern void intr18( void );
-extern void intr19( void );
-
-/* just to link with GNU tools JRS 09/22/2000 */
-asm (".global V_SPILL, V_FILL" );
-asm (".global V_EPI_OS, V_BSD_OS" );
-
-asm (".equ V_SPILL, 64" );
-asm (".equ V_FILL, 65" );
-
-asm (".equ V_BSD_OS, 66" );
-asm (".equ V_EPI_OS, 69" );
-
-/* end of just to link with GNU tools */
-
-void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-)
-{
- /*
- * This is where we install the interrupt handler into the "raw" interrupt
- * table used by the CPU to dispatch interrupt handlers.
- */
- switch( vector )
- {
-/* where is this code? JRS */
-#if 0
- case 14:
- _settrap( vector, intr14 );
- break;
- case 18:
- _settrap( vector, intr18 );
- break;
- case 19:
- _settrap( vector, intr19 );
- break;
-#endif
-
- default:
- break;
- }
-}
-
-
-/*PAGE
- *
- * _CPU_ISR_install_vector
- *
- * This kernel routine installs the RTEMS handler for the
- * specified vector.
- *
- * Input parameters:
- * vector - interrupt vector number
- * old_handler - former ISR for this vector number
- * new_handler - replacement ISR for this vector number
- *
- * Output parameters: NONE
- *
- */
-
-void _CPU_ISR_install_vector(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-)
-{
- *old_handler = _ISR_Vector_table[ vector ];
-
- /*
- * If the interrupt vector table is a table of pointer to isr entry
- * points, then we need to install the appropriate RTEMS interrupt
- * handler for this vector number.
- */
-
- _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
-
- /*
- * We put the actual user ISR address in '_ISR_vector_table'. This will
- * be used by the _ISR_Handler so the user gets control.
- */
-
- _ISR_Vector_table[ vector ] = new_handler;
-}
-
-/*PAGE
- *
- * _CPU_Install_interrupt_stack
- */
-
-void _CPU_Install_interrupt_stack( void )
-{
-}
-
-/*PAGE
- *
- * _CPU_Thread_Idle_body
- *
- * NOTES:
- *
- * 1. This is the same as the regular CPU independent algorithm.
- *
- * 2. If you implement this using a "halt", "idle", or "shutdown"
- * instruction, then don't forget to put it in an infinite loop.
- *
- * 3. Be warned. Some processors with onboard DMA have been known
- * to stop the DMA if the CPU were put in IDLE mode. This might
- * also be a problem with other on-chip peripherals. So use this
- * hook with caution.
- */
-
-void _CPU_Thread_Idle_body( void )
-{
-
- for( ; ; )
- {
- }
- /* insert your "halt" instruction here */ ;
-}
-
-void a29k_fatal_error( unsigned32 error )
-{
- printf("\n\nfatal error %d, rebooting!!!\n",error );
- exit(error);
-}
-
- /*
- * This discussion ignores a lot of the ugly details in a real
- * implementation such as saving enough registers/state to be
- * able to do something real. Keep in mind that the goal is
- * to invoke a user's ISR handler which is written in C and
- * uses a certain set of registers.
- *
- * Also note that the exact order is to a large extent flexible.
- * Hardware will dictate a sequence for a certain subset of
- * _ISR_Handler while requirements for setting
- */
-
- /*
- * At entry to "common" _ISR_Handler, the vector number must be
- * available. On some CPUs the hardware puts either the vector
- * number or the offset into the vector table for this ISR in a
- * known place. If the hardware does not give us this information,
- * then the assembly portion of RTEMS for this port will contain
- * a set of distinct interrupt entry points which somehow place
- * the vector number in a known place (which is safe if another
- * interrupt nests this one) and branches to _ISR_Handler.
- *
- */
-
-void a29k_ISR_Handler(unsigned32 vector)
-{
- _ISR_Nest_level++;
- _Thread_Dispatch_disable_level++;
- if ( _ISR_Vector_table[ vector ] )
- (*_ISR_Vector_table[ vector ])( vector );
- --_Thread_Dispatch_disable_level;
- --_ISR_Nest_level;
-
- if ( _ISR_Nest_level )
- return;
-
- if ( _Thread_Dispatch_disable_level ) {
- _ISR_Signals_to_thread_executing = FALSE;
- return;
- }
-
- if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
- _ISR_Signals_to_thread_executing = FALSE;
- _Thread_Dispatch();
- }
-}
diff --git a/cpukit/score/cpu/a29k/cpu_asm.S b/cpukit/score/cpu/a29k/cpu_asm.S
deleted file mode 100644
index cc35e79ee3..0000000000
--- a/cpukit/score/cpu/a29k/cpu_asm.S
+++ /dev/null
@@ -1,522 +0,0 @@
-;/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s
-; *
-; * Author: Craig Lebakken <craigl@transition.com>
-; *
-; * COPYRIGHT (c) 1996 by Transition Networks Inc.
-; *
-; * To anyone who acknowledges that this file is provided "AS IS"
-; * without any express or implied warranty:
-; * permission to use, copy, modify, and distribute this file
-; * for any purpose is hereby granted without fee, provided that
-; * the above copyright notice and this notice appears in all
-; * copies, and that the name of Transition Networks not be used in
-; * advertising or publicity pertaining to distribution of the
-; * software without specific, written prior permission.
-; * Transition Networks makes no representations about the suitability
-; * of this software for any purpose.
-; *
-; *
-; * This file contains the basic algorithms for all assembly code used
-; * in an specific CPU port of RTEMS. These algorithms must be implemented
-; * in assembly language
-; *
-; * NOTE: This is supposed to be a .S or .s file NOT a C file.
-; *
-; * COPYRIGHT (c) 1989-1999.
-; * On-Line Applications Research Corporation (OAR).
-; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.OARcorp.com/rtems/license.html.
-; *
-; * $Id$
-; */
-
-;/*
-; * This is supposed to be an assembly file. This means that system.h
-; * and cpu.h should not be included in a "real" cpu_asm file. An
-; * implementation in assembly should include "cpu_asm.h>
-; */
-
-;#include <cpu_asm.h>
-#include <register.ah>
-#include <amd.ah>
-#include <pswmacro.ah>
-; .extern _bsp_exit
-;
-; push a register onto the struct
- .macro spush, sp, reg
- store 0, 0, reg, sp ; push register
- add sp, sp, 4 ; adjust stack pointer
- .endm
-; push a register onto the struct
- .macro spushsr, sp, reg, sr
- mfsr reg, sr
- store 0, 0, reg, sp ; push register
- add sp, sp, 4 ; adjust stack pointer
- .endm
-; pop a register from the struct
- .macro spop, reg, sp
- load 0, 0, reg, sp
- add sp,sp,4
- .endm
-; pop a special register from the struct
- .macro spopsr, sreg, reg, sp
- load 0, 0, reg, sp
- mtsr sreg, reg
- add sp,sp,4
- .endm
-;
-;/*
-; * _CPU_Context_save_fp_context
-; *
-; * This routine is responsible for saving the FP context
-; * at *fp_context_ptr. If the point to load the FP context
-; * from is changed then the pointer is modified by this routine.
-; *
-; * Sometimes a macro implementation of this is in cpu.h which dereferences
-; * the ** and a similarly named routine in this file is passed something
-; * like a (Context_Control_fp *). The general rule on making this decision
-; * is to avoid writing assembly language.
-; */
-
-;#if 0
-;void _CPU_Context_save_fp(
-; void **fp_context_ptr
-;)
-;{
-;}
-;#endif
- .global _CPU_Context_save_fp
-_CPU_Context_save_fp:
- jmpi lr0
- nop
-
-;/*
-; * _CPU_Context_restore_fp_context
-; *
-; * This routine is responsible for restoring the FP context
-; * at *fp_context_ptr. If the point to load the FP context
-; * from is changed then the pointer is modified by this routine.
-; *
-; * Sometimes a macro implementation of this is in cpu.h which dereferences
-; * the ** and a similarly named routine in this file is passed something
-; * like a (Context_Control_fp *). The general rule on making this decision
-; * is to avoid writing assembly language.
-; */
-
-;#if 0
-;void _CPU_Context_restore_fp(
-; void **fp_context_ptr
-;)
-;{
-;}
-;#endif
- .global __CPU_Context_restore_fp
-__CPU_Context_restore_fp:
- jmpi lr0
- nop
-
-;/* _CPU_Context_switch
-; *
-; * This routine performs a normal non-FP context switch.
-; */
-;#if 0
-;void _CPU_Context_switch(
-; Context_Control *run,
-; Context_Control *heir
-;)
-;{
-;}
-;#endif
- .global __CPU_Context_switch
-__CPU_Context_switch:
- asneq 106, gr1, gr1 ; syscall
- jmpi lr0 ;
- nop ;
-
-
-
- .global _a29k_context_switch_sup
-_a29k_context_switch_sup:
-#if 0
- add pcb,lr2,0
- add kt1,lr3,0 ;move heir pointer to safe location
- constn it0,SIG_SYNC
- spush pcb,it0
- spush pcb,gr1
- spush pcb,rab ;push rab
- spushsr pcb,it0,pc0 ;push specials
- spushsr pcb,it0,pc1
- add pcb,pcb,1*4 ;space pc2
- spushsr pcb,it0,CHA ;push CHA
- spushsr pcb,it0,CHD ;push CHD
- spushsr pcb,it0,CHC ;push CHC
- add pcb,pcb,1*4 ;space for alu
- spushsr pcb,it0,ops ;push OPS
- mfsr kt0,cps ;current status
- const it1,FZ ;FZ constant
- andn it1,kt0,it1 ;clear FZ bit
- mtsr cps,it1 ;cps without FZ
- add pcb,pcb,1*4 ;space for tav
- mtsrim chc,0 ;possible DERR
-;
- spush pcb,lr1 ;push R-stack
- spush pcb,rfb ; support
- spush pcb,msp ;push M-stack pnt.
-;
- add pcb,pcb,3*4 ;space for floating point
-; spush pcb,FPStat0 ;floating point
-; spush pcb,FPStat1
-; spush pcb,FPStat2
-;
- add pcb,pcb,4*4 ;space for IPA..Q
-;
- mtsrim cr,29-1
- storem 0,0,gr96,pcb ;push gr96-124, optional
- add pcb,pcb,29*4 ;space for gr96-124
-;
- sub it0,rfb,gr1 ;get bytes in cache
- srl it0,it0,2 ;adjust to words
- sub it0,it0,1
- spush pcb,it0
- mtsr cr,it0
- storem 0,0,lr0,pcb ;save lr0-rfb
-;
-context_restore:
- add pcb,kt1,0 ;pcb=heir
- add pcb,pcb,4 ;space for signal num
- spop gr1,pcb ;restore freeze registers
- add gr1,gr1,0 ;alu op
- add pcb,pcb,9*4 ;move past freeze registers
- add pcb,pcb,1*4 ;space for tav
- spop lr1,pcb
- spop rfb,pcb
- spop msp,pcb
-; spop FPStat0,pcb
-; spop FPStat1,pcb
-; spop FPStat2,pcb
- add pcb,pcb,3*4 ;space for floating point
- add pcb,pcb,4*4 ;space for IPA..Q
- mtsrim cr,29-1
- loadm 0,0,gr96,pcb ;pop gr96-gr124
- add pcb,pcb,29*4 ;space for gr96-124
-
- spop it1,pcb ;pop locals count
- mtsr cr,it1
- loadm 0,0,lr0,pcb ;load locals
-
- add pcb,kt1,0 ;pcb=heir
- mtsr cps,kt0 ;cps with FZ
- nop
- add pcb,pcb,4 ;space for signal num
- spop gr1,pcb ;restore freeze registers
- add gr1,gr1,0 ;alu op
- spop rab,pcb
- spopsr pc0,it1,pcb
- spopsr pc1,it1,pcb
- add pcb,pcb,4 ;space for pc2
- spopsr CHA,it1,pcb
- spopsr CHD,it1,pcb
- spopsr CHC,it1,pcb
- add pcb,pcb,4 ;space for alu
- spopsr ops,it1,pcb
- nop
- iret
-#endif
-
-
-;/*
-; * _CPU_Context_restore
-; *
-; * This routine is generally used only to restart self in an
-; * efficient manner. It may simply be a label in _CPU_Context_switch.
-; *
-; * NOTE: May be unnecessary to reload some registers.
-; */
-;#if 0
-;void _CPU_Context_restore(
-; Context_Control *new_context
-;)
-;{
-;}
-;#endif
-
- .global __CPU_Context_restore
-__CPU_Context_restore:
-#if 0
- asneq 107, gr1, gr1 ; syscall
- jmpi lr0 ;
- nop ;
-
- .global _a29k_context_restore_sup
-_a29k_context_restore_sup:
- add kt1,lr2,0 ;kt1 = restore context
- mfsr kt0,cps ;current status
- const it1,FZ ;FZ constant
- andn it1,kt0,it1 ;clear FZ bit
- mtsr cps,it1 ;cps without FZ
- jmp context_restore
- nop
-
- .global _a29k_context_save_sup
-_a29k_context_save_sup:
- add pcb,lr2,0
- constn it0,SIG_SYNC
- spush pcb,it0
- spush pcb,gr1
- spush pcb,rab ;push rab
- spushsr pcb,it0,pc0 ;push specials
- spushsr pcb,it0,pc1
- add pcb,pcb,1*4 ;space pc2
- spushsr pcb,it0,CHA ;push CHA
- spushsr pcb,it0,CHD ;push CHD
- spushsr pcb,it0,CHC ;push CHC
- add pcb,pcb,1*4 ;space for alu
- spushsr pcb,it0,ops ;push OPS
- mfsr it0,cps ;current status
-SaveFZState it1,it2
- add pcb,pcb,1*4 ;space for tav
- mtsrim chc,0 ;possible DERR
-;
- spush pcb,lr1 ;push R-stack
- spush pcb,rfb ; support
- spush pcb,msp ;push M-stack pnt.
-;
- spush pcb,FPStat0 ;floating point
- spush pcb,FPStat1
- spush pcb,FPStat2
-;
- add pcb,pcb,4*4 ;space for IPA..Q
-;
- mtsrim cr,29-1
- storem 0,0,gr96,pcb ;push gr96-124, optional
- add pcb,pcb,29*4 ;space for gr96-124
-;
- sub kt0,rfb,gr1 ;get bytes in cache
- srl kt0,kt0,2 ;adjust to words
- sub kt0,kt0,1
- spush pcb,kt0 ;push number of words
- mtsr cr,kt0
- storem 0,0,lr0,pcb ;save lr0-rfb
-;
- mtsr cps,it0 ;cps with FZ
-RestoreFZState it1,it2
-
- nop
- nop
- nop
-;
- iret
-;
-#endif
-
- .global __CPU_Context_save
-__CPU_Context_save:
-#if 0
- asneq 108, gr1, gr1 ; syscall
- jmpi lr0 ;
- nop ;
-#endif
-
-
-;/* void __ISR_Handler()
-; *
-; * This routine provides the RTEMS interrupt management.
-; *
-; */
-
-;#if 0
-;void _ISR_Handler()
-;{
-; /*
-; * This discussion ignores a lot of the ugly details in a real
-; * implementation such as saving enough registers/state to be
-; * able to do something real. Keep in mind that the goal is
-; * to invoke a user's ISR handler which is written in C and
-; * uses a certain set of registers.
-; *
-; * Also note that the exact order is to a large extent flexible.
-; * Hardware will dictate a sequence for a certain subset of
-; * _ISR_Handler while requirements for setting
-; */
-
-; /*
-; * At entry to "common" _ISR_Handler, the vector number must be
-; * available. On some CPUs the hardware puts either the vector
-; * number or the offset into the vector table for this ISR in a
-; * known place. If the hardware does not give us this information,
-; * then the assembly portion of RTEMS for this port will contain
-; * a set of distinct interrupt entry points which somehow place
-; * the vector number in a known place (which is safe if another
-; * interrupt nests this one) and branches to _ISR_Handler.
-; *
-; * save some or all context on stack
-; * may need to save some special interrupt information for exit
-; *
-; * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
-; * if ( _ISR_Nest_level == 0 )
-; * switch to software interrupt stack
-; * #endif
-; *
-; * _ISR_Nest_level++;
-; *
-; * _Thread_Dispatch_disable_level++;
-; *
-; * (*_ISR_Vector_table[ vector ])( vector );
-; *
-; * --_ISR_Nest_level;
-; *
-; * if ( _ISR_Nest_level )
-; * goto the label "exit interrupt (simple case)"
-; *
-; * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
-; * restore stack
-; * #endif
-; *
-; * if ( !_Context_Switch_necessary )
-; * goto the label "exit interrupt (simple case)"
-; *
-; * if ( !_ISR_Signals_to_thread_executing )
-; * goto the label "exit interrupt (simple case)"
-; *
-; * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
-; *
-; * prepare to get out of interrupt
-; * return from interrupt (maybe to _ISR_Dispatch)
-; *
-; * LABEL "exit interrupt (simple case):
-; * prepare to get out of interrupt
-; * return from interrupt
-; */
-;}
-;#endif
-; .global __ISR_Handler
-;__ISR_Handler:
-; jmpi lr0
-; nop
-
- .global _a29k_getops
-_a29k_getops:
-#if 0
- asneq 113, gr96, gr96
- jmpi lr0
- nop
-#endif
-
- .global _a29k_getops_sup
-_a29k_getops_sup:
-#if 0
- mfsr gr96, ops ; caller wants ops
- iret
- nop
-#endif
-
- .global _a29k_disable
-_a29k_disable:
-#if 0
- asneq 110, gr96, gr96
- jmpi lr0
- nop
-#endif
-
- .global _a29k_disable_sup
-_a29k_disable_sup:
-#if 0
- mfsr kt0, ops
- add gr96, kt0, 0 ; return ops to caller
- const kt1, (DI | TD)
- consth kt1, (DI | TD)
- or kt1, kt0, kt1
- mtsr ops, kt1
- iret
- nop
-#endif
-
- .global _a29k_disable_all
-_a29k_disable_all:
-#if 0
- asneq 112, gr96, gr96
- jmpi lr0
- nop
-#endif
-
- .global _a29k_disable_all_sup
-_a29k_disable_all_sup:
-#if 0
- mfsr kt0, ops
- const kt1, (DI | TD)
- consth kt1, (DI | TD)
- or kt1, kt0, kt1
- mtsr ops, kt1
- iret
- nop
-#endif
-
- .global _a29k_enable_all
-_a29k_enable_all:
-#if 0
- asneq 111, gr96, gr96
- jmpi lr0
- nop
-#endif
-
- .global _a29k_enable_all_sup
-_a29k_enable_all_sup:
-#if 0
- mfsr kt0, ops
- const kt1, (DI | TD)
- consth kt1, (DI | TD)
- andn kt1, kt0, kt1
- mtsr ops, kt1
- iret
- nop
-#endif
-
- .global _a29k_enable
-_a29k_enable:
-#if 0
- asneq 109, gr96, gr96
- jmpi lr0
- nop
-#endif
-
- .global _a29k_enable_sup
-_a29k_enable_sup:
-#if 0
- mfsr kt0, ops
- const kt1, (DI | TD)
- consth kt1, (DI | TD)
- and kt3, lr2, kt1
- andn kt0, kt0, kt1
- or kt1, kt0, kt3
- mtsr ops, kt1
- iret
- nop
-#endif
-
- .global _a29k_halt
-_a29k_halt:
-#if 0
- halt
- jmp _a29k_halt
- nop
-#endif
-
- .global _a29k_super_mode
-_a29k_super_mode:
-#if 0
- mfsr gr96, ops
- or gr96, gr96, 0x10
- mtsr ops, gr96
- iret
- nop
-#endif
-
- .global _a29k_as70
-_a29k_as70:
-#if 0
- asneq 70,gr96,gr96
- jmpi lr0
- nop
-#endif
diff --git a/cpukit/score/cpu/a29k/pswmacro.ah b/cpukit/score/cpu/a29k/pswmacro.ah
deleted file mode 100644
index 12f6dc6abd..0000000000
--- a/cpukit/score/cpu/a29k/pswmacro.ah
+++ /dev/null
@@ -1,442 +0,0 @@
-; /* @(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI */
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; macros: Do_install and init_TLB
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; /* $Id$ */
-
-;* File information and includes.
-
- .file "macro.ah"
- .ident "@(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI"
-
-
- .macro CONST32, RegName, RegValue
- const RegName, RegValue
- consth RegName, RegValue
- .endm
-
- .macro CONSTX, RegName, RegValue
- .if (RegValue) <= 0x0000ffff
- const RegName, RegValue
- .else
- const RegName, RegValue
- consth RegName, RegValue
- .endif
- .endm
-
- .macro PRODEV, RegName
- srl RegName, RegName, 24
- .endm
-
-;
-;* MACRO TO INSTALL VECTOR TABLE ENTRIES
-;
-
-;* Assumes vector table address in v0
-
- .macro _setvec, trapnum, trapaddr
- mfsr v0, vab ;
- const v2, trapnum ;
- sll v1, v2, 2 ;
- add v1, v1, v0 ; v0 has location of vector tab
-
- const v2, trapaddr ;
- consth v2, trapaddr ;
- store 0, 0, v2, v1 ;
- nop ;
- .endm
-
- .macro syscall, name
- const tav, HIF_@name ;
- asneq V_SYSCALL, gr1, gr1 ;
- nop ;
- nop ;
- .endm
-
-
-
-;* MACRO TO INSTALL VECTOR TABLE ENTRIES
-
- .macro Do_Install, V_Number, V_Address
- const lr4, V_Address
- consth lr4, V_Address
- const lr3, V_Number * 4
- consth lr3, V_Number * 4
- call lr0, V_Install
- nop
- .endm
-
- .macro Do_InstallX, V_Number, V_Address
- const lr4, V_Address
- consth lr4, V_Address
- const lr3, V_Number * 4
- consth lr3, V_Number * 4
- call lr0, V_InstallX
- nop
- .endm
-
-
-
-; push a register onto the stack
- .macro pushreg, reg, sp
- sub sp, sp, 4 ; adjust stack pointer
- store 0, 0, reg, sp ; push register
- .endm
-
- .macro push, sp, reg
- sub sp, sp, 4
- store 0, 0, reg, sp
- .endm
-
-; pop the register from stack
- .macro popreg, reg, sp
- load 0, 0, reg, sp ; pop register
- add sp, sp, 4 ; adjust stack pointer
- .endm
- .macro pop, reg, sp
- load 0, 0, reg, sp
- add sp, sp, 4
- .endm
-
-; push a special register onto stack
- .macro pushspcl, spcl, tmpreg, sp
- sub sp, sp, 4 ; adjust stack pointer
- mfsr tmpreg, spcl ; get spcl reg
- store 0, 0, tmpreg, sp ; push onto stack
- .endm
-
- .macro pushsr, sp, reg, sreg
- mfsr reg, sreg
- sub sp, sp, 4
- store 0, 0, reg, sp
- .endm
-
-; pop a special register from stack
- .macro popspcl, spcl, tmpreg, sp
- load 0, 0, tmpreg, sp ; pop from stack
- add sp, sp, 4 ; adjust stack pointer
- mtsr spcl, tmpreg ; set spcl reg
- .endm
-
- .macro popsr, sreg, reg, sp
- load 0, 0, reg, sp
- add sp, sp, 4
- mtsr sreg, reg
- .endm
-
-;
-; save freeze mode registers on memory stack.
-;
-
- .macro SaveFZState, tmp1, tmp2
-
- ; save freeze mode registers.
-
- pushspcl pc0, tmp1, msp
- pushspcl pc1, tmp1, msp
- pushspcl alu, tmp1, msp
-
- pushspcl cha, tmp1, msp
- pushspcl chd, tmp1, msp
- pushspcl chc, tmp1, msp
-
- pushspcl ops, tmp1, msp
-
- ; turn freeze off
-
- const tmp2, FZ
- mfsr tmp1, cps
- andn tmp1, tmp1, tmp2
- mtsr cps, tmp1
- .endm
-
-; restore freeze mode registers from memory stack.
-
- .macro RestoreFZState, tmp1, tmp2
-
- ; turn freeze on
-
- const tmp2, (FZ|DI|DA)
- mfsr tmp1, cps
- or tmp1, tmp1, tmp2
- mtsr cps, tmp1
-
- ; restore freeze mode registers.
-
- popspcl ops, tmp1, msp
- popspcl chc, tmp1, msp
- popspcl chd, tmp1, msp
- popspcl cha, tmp1, msp
- popspcl alu, tmp1, msp
- popspcl pc1, tmp1, msp
- popspcl pc0, tmp1, msp
- .endm
-
-;
-;*
-;
- .equ WS, 512 ; window size
- .equ RALLOC, 4 * 4 ; stack alloc for C
- .equ SIGCTX_UM_SIZE, 40 * 4 ;
- .equ SIGCTX_RFB, (38) * 4 ; user mode saved
- .equ SIGCTX_SM_SIZE, 12 * 4 ;
- .equ SIGCTX_SIG, (11)*4 + SIGCTX_UM_SIZE ;
- .equ SIGCTX_GR1, (10)*4 + SIGCTX_UM_SIZE ;
- .equ SIGCTX_RAB, (9)*4 + SIGCTX_UM_SIZE ;
- .equ SIGCTX_PC0, (8)*4 + SIGCTX_UM_SIZE ;
- .equ SIGCTX_PC1, (7)*4 + SIGCTX_UM_SIZE ;
- .equ SIGCTX_PC2, (6)*4 + SIGCTX_UM_SIZE ;
- .equ SIGCTX_CHC, (3)*4 + SIGCTX_UM_SIZE ;
- .equ SIGCTX_OPS, (1)*4 + SIGCTX_UM_SIZE ;
- .equ SIGCTX_TAV, (0)*4 + SIGCTX_UM_SIZE ;
-
- .macro sup_sv
- add it2, trapreg, 0 ; transfer signal #
- sub msp, msp, 4 ;
- store 0, 0, it2, msp ; save signal number
- sub msp, msp, 4 ; push gr1
-
- store 0, 0, gr1, msp ;
- sub msp, msp, 4 ; push rab
- store 0, 0, rab, msp ;
- const it0, WS ; Window size
-
- sub rab, rfb, it0 ; set rab = rfb-512
- pushsr msp, it0, PC0 ; save program counter0
- pushsr msp, it0, PC1 ; save program counter1
- pushsr msp, it0, PC2 ; save program counter2
-
- pushsr msp, it0, CHA ; save channel address
- pushsr msp, it0, CHD ; save channel data
- pushsr msp, it0, CHC ; save channel control
- pushsr msp, it0, ALU ; save alu
-
- pushsr msp, it0, OPS ; save ops
- sub msp, msp, 4 ;
- store 0, 0, tav, msp ; push tav
- mtsrim chc, 0 ; no loadm/storem
-
- mfsr it0, ops ; get ops value
- const it1, (TD | DI) ; disable interrupts
- consth it1, (TD | DI) ; disable interrupts
- or it0, it0, it1 ; set bits
-
- mtsr ops, it0 ; set new ops
- const it0, _sigcode ; signal handler
- consth it0, _sigcode ; signal handler
- mtsr pc1, it0 ; store pc1
-
- add it1, it0, 4 ; next addr
- mtsr pc0, it1 ; store pc1 location
- iret ; return
- nop ; ALIGN
- .endm
-
- .macro sig_return
- mfsr it0, cps ; get processor status
- const it1, FZ|DA ; Freeze + traps disable
- or it0, it0, it1 ; to set FZ+DA
- mtsr cps, it0 ; in freeze mode
-
- load 0, 0, tav, msp ; restore tav
- add msp, msp, 4 ;
-
- popsr OPS,it0, msp ;
- popsr ALU,it0, msp ;
- popsr CHC,it0, msp ;
- popsr CHD,it0, msp ;
-
- popsr CHA,it0, msp ;
- popsr PC2,it0, msp ;
- popsr PC1,it0, msp ;
- popsr PC0,it0, msp ;
-
- load 0, 0, rab, msp ;
- add msp, msp, 4 ;
- load 0, 0, it0, msp ;
- add gr1, it0, 0 ; pop rsp
-
- add msp, msp, 8 ; discount signal #
- iret
- .endm
-
- .macro repair_R_stack
- add v0, msp, SIGCTX_GR1 ; interrupted gr1
- load 0, 0, v2, v0 ;
- add v0, msp, SIGCTX_RFB ;
- load 0, 0, v3, v0 ; interupted rfb
-
- const v1, WS ;
- sub v1, v3, v1 ; rfb-512
- cpltu v0, v2, v1 ; test gr1 < rfb-512
- jmpf v0, $1 ;
-
- add gr1, rab, 0 ;
- add v2, v1, 0 ; set LB = rfb-512
-$1:
-;* if gr1 < rfb-512 yes LB = rfb-512 signalled during spill
-;* if no, LB=gr1 interrupted cache < 126 registers
- cpleu v0, v2, rfb ; test LB<=rfb
- jmpf v0, $2 ;
- nop ;
- add v2, rfb, 0 ;
-$2:
- cpeq v0, v3, rfb ; fill rfb->rfb
- jmpt v0, $3 ; if rfb==rfb
- const tav, (0x80<<2) ; prepare for fill
- or tav, tav, v2 ;
-
- mtsr IPA, tav ; IPA=LA<<2
- sub tav, v3, gr98 ; cache fill LA->rfb
- srl tav, tav, 2 ; convert to words
- sub tav, tav, 1 ;
-
- mtsr cr, tav ;
- loadm 0, 0, gr0, v2 ; fill from LA->rfb
-$3:
- add rfb, v3, 0 ; move rfb upto rfb
- sub rab, v1, 0 ; assign rab to rfb-512
-
- add v0, msp, SIGCTX_GR1 ;
- load 0, 0, v2, v0 ; v0 = interrupted gr1
- add gr1, v2, 0 ; move gr1 upto gr1
- nop ;
- .endm
-
- .macro repair_regs
- mtsrim cr, 29 - 1 ; to restore locals
- loadm 0, 0, v0, msp ;
- add msp, msp, 29*4 ;
- popsr Q, tav, msp ;
-
- popsr IPC, tav, msp ;
- popsr IPB, tav, msp ;
- popsr IPA, tav, msp ;
- pop FPStat3, msp ; floating point regs
-
- pop FPStat2, msp ; floating point regs
- pop FPStat1, msp ; floating point regs
- pop FPStat0, msp ; floating point regs
-
- add msp, msp, 3*4 ; R-stack repaired
- .endm
-
-;
-;*HIF related...
-;
-
-
-
-
-; send the message in bufaddr to Montip.
- .macro SendMessageToMontip, bufaddr
- const lr2, bufaddr
-$1:
- call lr0, _msg_send
- consth lr2, bufaddr
- cpeq gr96, gr96, 0
- jmpf gr96, $1
- const lr2, bufaddr
- .endm
-
-; build a HIF_CALL message in bufaddr to send to montip.
- .macro BuildHIFCALLMsg, bufaddr, tmp1, tmp2
- const tmp1, bufaddr
- consth tmp1, bufaddr
- const tmp2, HIF_CALL_MSGCODE
- store 0, 0, tmp2, tmp1 ; msg code
- add tmp1, tmp1, 4
- const tmp2, HIF_CALL_MSGLEN
- store 0, 0, tmp2, tmp1 ; msg len
- add tmp1, tmp1, 4
- store 0, 0, gr121, tmp1 ; service number
- add tmp1, tmp1, 4
- store 0, 0, lr2, tmp1 ; lr2
- add tmp1, tmp1, 4
- store 0, 0, lr3, tmp1 ; lr3
- add tmp1, tmp1, 4
- store 0, 0, lr4, tmp1 ; lr4
- .endm
-
-;
-;*
-;* All the funky AMD style macros go in here...simply for
-;* compatility
-;
-;
- .macro IMPORT, symbol
- .extern symbol
- .endm
-
- .macro GLOBAL, symbol
- .global symbol
- .endm
-
- .macro USESECT, name, type
- .sect name, type
- .use name
- .endm
-
- .macro SECTION, name, type
- .sect name, type
- .endm
-
- .macro FUNC, fname, lineno
- .global fname
-fname:
- .endm
-
- .macro ENDFUNC, fname, lineno
- .endm
-
-;*************************************LONG
- .macro LONG, varname
-varname:
- .block 4
- .endm
-
-;*************************************UNSIGNED LONG
- .macro ULONG, varname
-varname:
- .block 4
- .endm
-
-;*************************************SHORT
- .macro SHORT, varname
-varname:
- .block 2
- .endm
-
-;*************************************CHAR
- .macro CHAR, varname
-varname:
- .block 1
- .endm
-
-;*************************************LONGARRAY
- .macro LONGARRAY, name, count
-name:
- .block count*4
- .endm
-
-;*************************************SHORTARRAY
-
- .macro SHORTARRAY, name, count
-name:
- .block count*2
- .endm
-
-;*************************************CHARARRAY
-
- .macro CHARARRAY, name, count
-name:
- .block count
- .endm
-
-
-;*************************************VOID_FPTR
-
- .macro VOID_FPTR, name
-name:
- .block 4
- .endm
diff --git a/cpukit/score/cpu/a29k/register.ah b/cpukit/score/cpu/a29k/register.ah
deleted file mode 100644
index 853e6ef049..0000000000
--- a/cpukit/score/cpu/a29k/register.ah
+++ /dev/null
@@ -1,217 +0,0 @@
-; /* @(#)register.ah 1.1 96/05/23 08:56:57, TEI */
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; naming of various registers
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; /* $Id$ */
-
-;* File information and includes.
-
- .file "register.ah"
- .ident "@(#)register.ah 1.1 96/05/23 08:56:57, TEI\n"
-
-;* Register Stack pointer and frame pointer registers.
-
-/* The assembly language is supposed to be Sierra High-C */
-#if 0
- .extern Rrsp, Rfp
-
- .reg regsp, %%Rrsp
- .reg fp, %%Rfp
-
-
- .extern RTrapReg
- .extern Rtrapreg
-
- .reg TrapReg, %%RTrapReg
- .reg trapreg, %%Rtrapreg
-
-
-;* Operating system Interrupt handler registers (gr64-gr67)
-
- .extern ROSint0, ROSint1, ROSint2, ROSint3
-
- .reg OSint0, %%ROSint0
- .reg OSint1, %%ROSint1
- .reg OSint2, %%ROSint2
- .reg OSint3, %%ROSint3
-
- .reg it0, %%ROSint0
- .reg it1, %%ROSint1
- .reg it2, %%ROSint2
- .reg it3, %%ROSint3
-
-
-
-;* Operating system temporary (or scratch) registers (gr68-gr79)
-
- .extern ROStmp0, ROStmp1, ROStmp2, ROStmp3
- .extern ROStmp4, ROStmp5, ROStmp6, ROStmp7
- .extern ROStmp8, ROStmp9, ROStmp10, ROStmp11
-
- .reg OStmp0, %%ROStmp0
- .reg OStmp1, %%ROStmp1
- .reg OStmp2, %%ROStmp2
- .reg OStmp3, %%ROStmp3
-
- .reg OStmp4, %%ROStmp4
- .reg OStmp5, %%ROStmp5
- .reg OStmp6, %%ROStmp6
- .reg OStmp7, %%ROStmp7
-
- .reg OStmp8, %%ROStmp8
- .reg OStmp9, %%ROStmp9
- .reg OStmp10, %%ROStmp10
- .reg OStmp11, %%ROStmp11
-
-
- .reg kt0, %%ROStmp0
- .reg kt1, %%ROStmp1
- .reg kt2, %%ROStmp2
- .reg kt3, %%ROStmp3
-
- .reg kt4, %%ROStmp4
- .reg kt5, %%ROStmp5
- .reg kt6, %%ROStmp6
- .reg kt7, %%ROStmp7
-
- .reg kt8, %%ROStmp8
- .reg kt9, %%ROStmp9
- .reg kt10, %%ROStmp10
- .reg kt11, %%ROStmp11
-
-
- .reg TempReg0, %%ROSint0
- .reg TempReg1, %%ROSint1
- .reg TempReg2, %%ROSint2
- .reg TempReg3, %%ROSint3
-
- .reg TempReg4, %%ROStmp0
- .reg TempReg5, %%ROStmp1
- .reg TempReg6, %%ROStmp2
- .reg TempReg7, %%ROStmp3
-
- .reg TempReg8, %%ROStmp4
- .reg TempReg9, %%ROStmp5
- .reg TempReg10, %%ROStmp6
- .reg TempReg11, %%ROStmp7
-
- .reg TempReg12, %%ROStmp8
- .reg TempReg13, %%ROStmp9
- .reg TempReg14, %%ROStmp10
- .reg TempReg15, %%ROStmp11
-
-
-;* Assigned static registers
-
- .extern RSpillAddrReg, RFillAddrReg, RSignalAddrReg
- .extern Rpcb, Retc
- .extern RTimerExt, RTimerUtil, RLEDReg, RERRReg
- .extern Ret0, Ret1, Ret2, Ret3, Ret4, Ret5, Ret6, Ret7, Reta, Retb
- .extern Retx, Rety, Retz
-
-
- .reg SpillAddrReg, %%RSpillAddrReg
- .reg FillAddrReg, %%RFillAddrReg
- .reg SignalAddrReg, %%RSignalAddrReg
- .reg pcb, %%Rpcb
-
- .reg etx, %%Retx
- .reg ety, %%Rety
- .reg etz, %%Retz
- .reg eta, %%Reta
-
- .reg etb, %%Retb
- .reg etc, %%Retc
- .reg TimerExt, %%RTimerExt
- .reg TimerUtil, %%RTimerUtil
-
- .reg LEDReg, %%RLEDReg
- .reg ERRReg, %%RERRReg
-
-
- .reg et0, %%Ret0
- .reg et1, %%Ret1
- .reg et2, %%Ret2
- .reg et3, %%Ret3
-
- .reg et4, %%Ret4
- .reg et5, %%Ret5
- .reg et6, %%Ret6
- .reg et7, %%Ret7
-
-;
- .equ SCB1REG_NUM, 88
- .reg SCB1REG_PTR, %%Ret0
-
-; The floating point trap handlers need a few static registers
-
- .extern RFPStat0, RFPStat1, RFPStat2, RFPStat3
- .extern Rheapptr, RHeapPtr, RArgvPtr
-
- .reg FPStat0, %%RFPStat0
- .reg FPStat1, %%RFPStat1
- .reg FPStat2, %%RFPStat2
- .reg FPStat3, %%RFPStat3
-
- .reg heapptr, %%Rheapptr
- .reg HeapPtr, %%RHeapPtr
- .reg ArgvPtr, %%RArgvPtr
-
- .extern RXLINXReg, RVMBCReg, RUARTReg, RETHERReg
-
- .reg XLINXReg, %%RXLINXReg
- .reg VMBCReg, %%RVMBCReg
- .reg UARTReg, %%RUARTReg
- .reg ETHERReg, %%RXLINXReg
-
-;* Compiler and programmer registers. (gr96-gr127)
-
- .extern Rv0, Rv1, Rv2, Rv3, Rv4, Rv5, Rv6, Rv7, Rv8, Rv9
- .extern Rv10, Rv11, Rv12, Rv13, Rv14, Rv15
-
- .reg v0, %%Rv0
- .reg v1, %%Rv1
- .reg v2, %%Rv2
- .reg v3, %%Rv3
-
- .reg v4, %%Rv4
- .reg v5, %%Rv5
- .reg v6, %%Rv6
- .reg v7, %%Rv7
-
- .reg v8, %%Rv8
- .reg v9, %%Rv9
- .reg v10, %%Rv10
- .reg v11, %%Rv11
-
- .reg v12, %%Rv12
- .reg v13, %%Rv13
- .reg v14, %%Rv14
- .reg v15, %%Rv15
-
- .extern Rtv0, Rtv1, Rtv2, Rtv3, Rtv4
-
- .reg tv0, %%Rtv0
- .reg tv1, %%Rtv1
- .reg tv2, %%Rtv2
- .reg tv3, %%Rtv3
- .reg tv4, %%Rtv4
-
-; ****************************************************************************
-; For uatrap
-; register definitions -- since this trap handler must allow for
-; nested traps and interrupts such as TLB miss, protection violation,
-; or Data Access Exception, and these trap handlers use the shared
-; Temp registers, we must maintain our own that are safe over user-
-; mode loads and stores. The following must be assigned global
-; registers which are not used in INTR[0-3], TRAP[0-1], TLB miss,
-; TLB protection violation, or data exception trap handlers.
-
-; .reg cha_cpy, OStmp4 ; copy of CHA
-; .reg chd_cpy, OStmp5 ; copy of CHD
-; .reg chc_cpy, OStmp6 ; copy of CHC
-; .reg LTemp0, OStmp7 ; local temp 0
-; .reg LTemp1, OStmp8 ; local temp 1
-
-; ****************************************************************************
-#endif
diff --git a/cpukit/score/cpu/a29k/rtems/.cvsignore b/cpukit/score/cpu/a29k/rtems/.cvsignore
deleted file mode 100644
index 282522db03..0000000000
--- a/cpukit/score/cpu/a29k/rtems/.cvsignore
+++ /dev/null
@@ -1,2 +0,0 @@
-Makefile
-Makefile.in
diff --git a/cpukit/score/cpu/a29k/rtems/score/.cvsignore b/cpukit/score/cpu/a29k/rtems/score/.cvsignore
deleted file mode 100644
index 282522db03..0000000000
--- a/cpukit/score/cpu/a29k/rtems/score/.cvsignore
+++ /dev/null
@@ -1,2 +0,0 @@
-Makefile
-Makefile.in
diff --git a/cpukit/score/cpu/a29k/rtems/score/a29k.h b/cpukit/score/cpu/a29k/rtems/score/a29k.h
deleted file mode 100644
index 99a2626202..0000000000
--- a/cpukit/score/cpu/a29k/rtems/score/a29k.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* a29k.h
- *
- * COPYRIGHT (c) 1989-1999.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- *
- */
-/* @(#)a29k.h 10/21/96 1.3 */
-
-#ifndef _INCLUDE_A29K_h
-#define _INCLUDE_A29K_h
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * This file contains the information required to build
- * RTEMS for a particular member of the "no cpu"
- * family when executing in protected mode. It does
- * this by setting variables to indicate which implementation
- * dependent features are present in a particular member
- * of the family.
- */
-
-#define A29K_HAS_FPU 0
-#define CPU_MODEL_NAME "a29xxx"
-
-/*
- * Moving toward multilib with no attempt to distinguish
- * multilib features in gcc.
- */
-
-#if 0
-#if defined(rtems_multilib)
-/*
- * Figure out all CPU Model Feature Flags based upon compiler
- * predefines.
- */
-
-#define CPU_MODEL_NAME "rtems_multilib"
-#define A29K_HAS_FPU 0
-
-#elif defined(a29205)
-
-#define CPU_MODEL_NAME "a29205"
-#define A29K_HAS_FPU 0
-
-#else
-
-#error "Unsupported CPU Model"
-
-#endif
-#endif
-
-/*
- * Define the name of the CPU family.
- */
-
-#define CPU_NAME "AMD 29K"
-
-/*
- * Some bits in the CPS:
- */
-#define TD 0x20000
-#define DI 0x00002
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ! _INCLUDE_A29K_h */
-/* end of include file */
diff --git a/cpukit/score/cpu/a29k/rtems/score/cpu.h b/cpukit/score/cpu/a29k/rtems/score/cpu.h
deleted file mode 100644
index 10c7be3b3f..0000000000
--- a/cpukit/score/cpu/a29k/rtems/score/cpu.h
+++ /dev/null
@@ -1,1008 +0,0 @@
-/* cpu.h
- *
- * This include file contains information pertaining to the AMD 29K
- * processor.
- *
- * Author: Craig Lebakken <craigl@transition.com>
- *
- * COPYRIGHT (c) 1996 by Transition Networks Inc.
- *
- * To anyone who acknowledges that this file is provided "AS IS"
- * without any express or implied warranty:
- * permission to use, copy, modify, and distribute this file
- * for any purpose is hereby granted without fee, provided that
- * the above copyright notice and this notice appears in all
- * copies, and that the name of Transition Networks not be used in
- * advertising or publicity pertaining to distribution of the
- * software without specific, written prior permission.
- * Transition Networks makes no representations about the suitability
- * of this software for any purpose.
- *
- * Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.c:
- *
- * COPYRIGHT (c) 1989-1999.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-/* @(#)cpu.h 10/21/96 1.11 */
-
-#ifndef __CPU_h
-#define __CPU_h
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtems/score/a29k.h> /* pick up machine definitions */
-#ifndef ASM
-#include <rtems/score/types.h>
-#endif
-
-extern unsigned int a29k_disable( void );
-extern void a29k_enable( unsigned int cookie );
-extern unsigned int a29k_getops( void );
-extern void a29k_getops_sup( void );
-extern void a29k_disable_sup( void );
-extern void a29k_enable_sup( void );
-extern void a29k_disable_all( void );
-extern void a29k_disable_all_sup( void );
-extern void a29k_enable_all( void );
-extern void a29k_enable_all_sup( void );
-extern void a29k_halt( void );
-extern void a29k_fatal_error( unsigned32 error );
-extern void a29k_as70( void );
-extern void a29k_super_mode( void );
-extern void a29k_context_switch_sup(void);
-extern void a29k_context_restore_sup(void);
-extern void a29k_context_save_sup(void);
-extern void a29k_sigdfl_sup(void);
-
-/* conditional compilation parameters */
-
-/*
- * Should the calls to _Thread_Enable_dispatch be inlined?
- *
- * If TRUE, then they are inlined.
- * If FALSE, then a subroutine call is made.
- *
- * Basically this is an example of the classic trade-off of size
- * versus speed. Inlining the call (TRUE) typically increases the
- * size of RTEMS while speeding up the enabling of dispatching.
- * [NOTE: In general, the _Thread_Dispatch_disable_level will
- * only be 0 or 1 unless you are in an interrupt handler and that
- * interrupt handler invokes the executive.] When not inlined
- * something calls _Thread_Enable_dispatch which in turns calls
- * _Thread_Dispatch. If the enable dispatch is inlined, then
- * one subroutine call is avoided entirely.]
- */
-
-#define CPU_INLINE_ENABLE_DISPATCH TRUE
-
-/*
- * Should the body of the search loops in _Thread_queue_Enqueue_priority
- * be unrolled one time? In unrolled each iteration of the loop examines
- * two "nodes" on the chain being searched. Otherwise, only one node
- * is examined per iteration.
- *
- * If TRUE, then the loops are unrolled.
- * If FALSE, then the loops are not unrolled.
- *
- * The primary factor in making this decision is the cost of disabling
- * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
- * body of the loop. On some CPUs, the flash is more expensive than
- * one iteration of the loop body. In this case, it might be desirable
- * to unroll the loop. It is important to note that on some CPUs, this
- * code is the longest interrupt disable period in RTEMS. So it is
- * necessary to strike a balance when setting this parameter.
- */
-
-#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
-
-/*
- * Does RTEMS manage a dedicated interrupt stack in software?
- *
- * If TRUE, then a stack is allocated in _ISR_Handler_initialization.
- * If FALSE, nothing is done.
- *
- * If the CPU supports a dedicated interrupt stack in hardware,
- * then it is generally the responsibility of the BSP to allocate it
- * and set it up.
- *
- * If the CPU does not support a dedicated interrupt stack, then
- * the porter has two options: (1) execute interrupts on the
- * stack of the interrupted task, and (2) have RTEMS manage a dedicated
- * interrupt stack.
- *
- * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
- *
- * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
- * possible that both are FALSE for a particular CPU. Although it
- * is unclear what that would imply about the interrupt processing
- * procedure on that CPU.
- */
-
-#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
-
-/*
- * Does this CPU have hardware support for a dedicated interrupt stack?
- *
- * If TRUE, then it must be installed during initialization.
- * If FALSE, then no installation is performed.
- *
- * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
- *
- * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
- * possible that both are FALSE for a particular CPU. Although it
- * is unclear what that would imply about the interrupt processing
- * procedure on that CPU.
- */
-
-#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
-
-/*
- * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
- *
- * If TRUE, then the memory is allocated during initialization.
- * If FALSE, then the memory is allocated during initialization.
- *
- * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
- * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
- */
-
-#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
-
-/*
- * Does the RTEMS invoke the user's ISR with the vector number and
- * a pointer to the saved interrupt frame (1) or just the vector
- * number (0)?
- */
-
-#define CPU_ISR_PASSES_FRAME_POINTER 0
-
-/*
- * Does the CPU have hardware floating point?
- *
- * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
- * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
- *
- * If there is a FP coprocessor such as the i387 or mc68881, then
- * the answer is TRUE.
- *
- * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
- * It indicates whether or not this CPU model has FP support. For
- * example, it would be possible to have an i386_nofp CPU model
- * which set this to false to indicate that you have an i386 without
- * an i387 and wish to leave floating point support out of RTEMS.
- */
-
-#if ( A29K_HAS_FPU == 1 )
-#define CPU_HARDWARE_FP TRUE
-#else
-#define CPU_HARDWARE_FP FALSE
-#endif
-#define CPU_SOFTWARE_FP FALSE
-
-/*
- * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
- *
- * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
- * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
- *
- * So far, the only CPU in which this option has been used is the
- * HP PA-RISC. The HP C compiler and gcc both implicitly use the
- * floating point registers to perform integer multiplies. If
- * a function which you would not think utilize the FP unit DOES,
- * then one can not easily predict which tasks will use the FP hardware.
- * In this case, this option should be TRUE.
- *
- * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
- */
-
-#define CPU_ALL_TASKS_ARE_FP FALSE
-
-/*
- * Should the IDLE task have a floating point context?
- *
- * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
- * and it has a floating point context which is switched in and out.
- * If FALSE, then the IDLE task does not have a floating point context.
- *
- * Setting this to TRUE negatively impacts the time required to preempt
- * the IDLE task from an interrupt because the floating point context
- * must be saved as part of the preemption.
- */
-
-#define CPU_IDLE_TASK_IS_FP FALSE
-
-/*
- * Should the saving of the floating point registers be deferred
- * until a context switch is made to another different floating point
- * task?
- *
- * If TRUE, then the floating point context will not be stored until
- * necessary. It will remain in the floating point registers and not
- * disturned until another floating point task is switched to.
- *
- * If FALSE, then the floating point context is saved when a floating
- * point task is switched out and restored when the next floating point
- * task is restored. The state of the floating point registers between
- * those two operations is not specified.
- *
- * If the floating point context does NOT have to be saved as part of
- * interrupt dispatching, then it should be safe to set this to TRUE.
- *
- * Setting this flag to TRUE results in using a different algorithm
- * for deciding when to save and restore the floating point context.
- * The deferred FP switch algorithm minimizes the number of times
- * the FP context is saved and restored. The FP context is not saved
- * until a context switch is made to another, different FP task.
- * Thus in a system with only one FP task, the FP context will never
- * be saved or restored.
- */
-
-#define CPU_USE_DEFERRED_FP_SWITCH TRUE
-
-/*
- * Does this port provide a CPU dependent IDLE task implementation?
- *
- * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
- * must be provided and is the default IDLE thread body instead of
- * _Internal_threads_Idle_thread_body.
- *
- * If FALSE, then use the generic IDLE thread body if the BSP does
- * not provide one.
- *
- * This is intended to allow for supporting processors which have
- * a low power or idle mode. When the IDLE thread is executed, then
- * the CPU can be powered down.
- *
- * The order of precedence for selecting the IDLE thread body is:
- *
- * 1. BSP provided
- * 2. CPU dependent (if provided)
- * 3. generic (if no BSP and no CPU dependent)
- */
-
-#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
-
-/*
- * Does the stack grow up (toward higher addresses) or down
- * (toward lower addresses)?
- *
- * If TRUE, then the grows upward.
- * If FALSE, then the grows toward smaller addresses.
- */
-
-#define CPU_STACK_GROWS_UP FALSE
-
-/*
- * The following is the variable attribute used to force alignment
- * of critical RTEMS structures. On some processors it may make
- * sense to have these aligned on tighter boundaries than
- * the minimum requirements of the compiler in order to have as
- * much of the critical data area as possible in a cache line.
- *
- * The placement of this macro in the declaration of the variables
- * is based on the syntactically requirements of the GNU C
- * "__attribute__" extension. For example with GNU C, use
- * the following to force a structures to a 32 byte boundary.
- *
- * __attribute__ ((aligned (32)))
- *
- * NOTE: Currently only the Priority Bit Map table uses this feature.
- * To benefit from using this, the data must be heavily
- * used so it will stay in the cache and used frequently enough
- * in the executive to justify turning this on.
- */
-
-#define CPU_STRUCTURE_ALIGNMENT
-
-/*
- * Define what is required to specify how the network to host conversion
- * routines are handled.
- *
- */
-
-/* #warning "Check these definitions!!!" */
-
-#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
-#define CPU_BIG_ENDIAN TRUE
-#define CPU_LITTLE_ENDIAN FALSE
-
-/*
- * The following defines the number of bits actually used in the
- * interrupt field of the task mode. How those bits map to the
- * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
- */
-
-#define CPU_MODES_INTERRUPT_MASK 0x00000001
-
-/*
- * Processor defined structures
- *
- * Examples structures include the descriptor tables from the i386
- * and the processor control structure on the i960ca.
- */
-
-/* may need to put some structures here. */
-
-/*
- * Contexts
- *
- * Generally there are 2 types of context to save.
- * 1. Interrupt registers to save
- * 2. Task level registers to save
- *
- * This means we have the following 3 context items:
- * 1. task level context stuff:: Context_Control
- * 2. floating point task stuff:: Context_Control_fp
- * 3. special interrupt level context :: Context_Control_interrupt
- *
- * On some processors, it is cost-effective to save only the callee
- * preserved registers during a task context switch. This means
- * that the ISR code needs to save those registers which do not
- * persist across function calls. It is not mandatory to make this
- * distinctions between the caller/callee saves registers for the
- * purpose of minimizing context saved during task switch and on interrupts.
- * If the cost of saving extra registers is minimal, simplicity is the
- * choice. Save the same context on interrupt entry as for tasks in
- * this case.
- *
- * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
- * care should be used in designing the context area.
- *
- * On some CPUs with hardware floating point support, the Context_Control_fp
- * structure will not be used or it simply consist of an array of a
- * fixed number of bytes. This is done when the floating point context
- * is dumped by a "FP save context" type instruction and the format
- * is not really defined by the CPU. In this case, there is no need
- * to figure out the exact format -- only the size. Of course, although
- * this is enough information for RTEMS, it is probably not enough for
- * a debugger such as gdb. But that is another problem.
- */
-
-typedef struct {
- unsigned32 signal;
- unsigned32 gr1;
- unsigned32 rab;
- unsigned32 PC0;
- unsigned32 PC1;
- unsigned32 PC2;
- unsigned32 CHA;
- unsigned32 CHD;
- unsigned32 CHC;
- unsigned32 ALU;
- unsigned32 OPS;
- unsigned32 tav;
- unsigned32 lr1;
- unsigned32 rfb;
- unsigned32 msp;
-
- unsigned32 FPStat0;
- unsigned32 FPStat1;
- unsigned32 FPStat2;
- unsigned32 IPA;
- unsigned32 IPB;
- unsigned32 IPC;
- unsigned32 Q;
-
- unsigned32 gr96;
- unsigned32 gr97;
- unsigned32 gr98;
- unsigned32 gr99;
- unsigned32 gr100;
- unsigned32 gr101;
- unsigned32 gr102;
- unsigned32 gr103;
- unsigned32 gr104;
- unsigned32 gr105;
- unsigned32 gr106;
- unsigned32 gr107;
- unsigned32 gr108;
- unsigned32 gr109;
- unsigned32 gr110;
- unsigned32 gr111;
-
- unsigned32 gr112;
- unsigned32 gr113;
- unsigned32 gr114;
- unsigned32 gr115;
-
- unsigned32 gr116;
- unsigned32 gr117;
- unsigned32 gr118;
- unsigned32 gr119;
- unsigned32 gr120;
- unsigned32 gr121;
- unsigned32 gr122;
- unsigned32 gr123;
- unsigned32 gr124;
-
- unsigned32 local_count;
-
- unsigned32 locals[128];
-} Context_Control;
-
-typedef struct {
- double some_float_register;
-} Context_Control_fp;
-
-typedef struct {
- unsigned32 special_interrupt_register;
-} CPU_Interrupt_frame;
-
-
-/*
- * The following table contains the information required to configure
- * the a29K processor specific parameters.
- *
- * NOTE: The interrupt_stack_size field is required if
- * CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
- *
- * The pretasking_hook, predriver_hook, and postdriver_hook,
- * and the do_zero_of_workspace fields are required on ALL CPUs.
- */
-
-typedef struct {
- void (*pretasking_hook)( void );
- void (*predriver_hook)( void );
- void (*postdriver_hook)( void );
- void (*idle_task)( void );
- boolean do_zero_of_workspace;
- unsigned32 idle_task_stack_size;
- unsigned32 interrupt_stack_size;
- unsigned32 extra_mpci_receive_server_stack;
- void * (*stack_allocate_hook)( unsigned32 );
- void (*stack_free_hook)( void* );
- /* end of fields required on all CPUs */
-
-} rtems_cpu_table;
-
-/*
- * Macros to access required entires in the CPU Table are in
- * the file rtems/system.h.
- */
-
-/*
- * Macros to access AMD A29K specific additions to the CPU Table
- */
-
-/* There are no CPU specific additions to the CPU Table for this port. */
-
-/*
- * This variable is optional. It is used on CPUs on which it is difficult
- * to generate an "uninitialized" FP context. It is filled in by
- * _CPU_Initialize and copied into the task's FP context area during
- * _CPU_Context_Initialize.
- */
-
-SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
-
-/*
- * On some CPUs, RTEMS supports a software managed interrupt stack.
- * This stack is allocated by the Interrupt Manager and the switch
- * is performed in _ISR_Handler. These variables contain pointers
- * to the lowest and highest addresses in the chunk of memory allocated
- * for the interrupt stack. Since it is unknown whether the stack
- * grows up or down (in general), this give the CPU dependent
- * code the option of picking the version it wants to use.
- *
- * NOTE: These two variables are required if the macro
- * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
- */
-
-SCORE_EXTERN void *_CPU_Interrupt_stack_low;
-SCORE_EXTERN void *_CPU_Interrupt_stack_high;
-
-/*
- * With some compilation systems, it is difficult if not impossible to
- * call a high-level language routine from assembly language. This
- * is especially true of commercial Ada compilers and name mangling
- * C++ ones. This variable can be optionally defined by the CPU porter
- * and contains the address of the routine _Thread_Dispatch. This
- * can make it easier to invoke that routine at the end of the interrupt
- * sequence (if a dispatch is necessary).
- */
-
-SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
-
-/*
- * Nothing prevents the porter from declaring more CPU specific variables.
- */
-
-/* XXX: if needed, put more variables here */
-
-/*
- * The size of the floating point context area. On some CPUs this
- * will not be a "sizeof" because the format of the floating point
- * area is not defined -- only the size is. This is usually on
- * CPUs with a "floating point save context" instruction.
- */
-
-#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
-
-/*
- * extra stack required by the MPCI receive server thread
- */
-
-#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
-
-/*
- * This defines the number of entries in the ISR_Vector_table managed
- * by RTEMS.
- */
-
-#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
-#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
-
-/*
- * This is defined if the port has a special way to report the ISR nesting
- * level. Most ports maintain the variable _ISR_Nest_level.
- */
-
-#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
-
-/*
- * Should be large enough to run all RTEMS tests. This insures
- * that a "reasonable" small application should not have any problems.
- */
-
-#define CPU_STACK_MINIMUM_SIZE (8192)
-
-/*
- * CPU's worst alignment requirement for data types on a byte boundary. This
- * alignment does not take into account the requirements for the stack.
- */
-
-#define CPU_ALIGNMENT 4
-
-/*
- * This number corresponds to the byte alignment requirement for the
- * heap handler. This alignment requirement may be stricter than that
- * for the data types alignment specified by CPU_ALIGNMENT. It is
- * common for the heap to follow the same alignment requirement as
- * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
- * then this should be set to CPU_ALIGNMENT.
- *
- * NOTE: This does not have to be a power of 2. It does have to
- * be greater or equal to than CPU_ALIGNMENT.
- */
-
-#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
-
-/*
- * This number corresponds to the byte alignment requirement for memory
- * buffers allocated by the partition manager. This alignment requirement
- * may be stricter than that for the data types alignment specified by
- * CPU_ALIGNMENT. It is common for the partition to follow the same
- * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict
- * enough for the partition, then this should be set to CPU_ALIGNMENT.
- *
- * NOTE: This does not have to be a power of 2. It does have to
- * be greater or equal to than CPU_ALIGNMENT.
- */
-
-#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
-
-/*
- * This number corresponds to the byte alignment requirement for the
- * stack. This alignment requirement may be stricter than that for the
- * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT
- * is strict enough for the stack, then this should be set to 0.
- *
- * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
- */
-
-#define CPU_STACK_ALIGNMENT 0
-
-/* ISR handler macros */
-
-/*
- * Support routine to initialize the RTEMS vector table after it is allocated.
- */
-
-#define _CPU_Initialize_vectors()
-
-/*
- * Disable all interrupts for an RTEMS critical section. The previous
- * level is returned in _level.
- */
-
-#define _CPU_ISR_Disable( _isr_cookie ) \
- do{ _isr_cookie = a29k_disable(); }while(0)
-
-/*
- * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- * This indicates the end of an RTEMS critical section. The parameter
- * _level is not modified.
- */
-
-#define _CPU_ISR_Enable( _isr_cookie ) \
- do{ a29k_enable(_isr_cookie) ; }while(0)
-
-/*
- * This temporarily restores the interrupt to _level before immediately
- * disabling them again. This is used to divide long RTEMS critical
- * sections into two or more parts. The parameter _level is not
- * modified.
- */
-
-#define _CPU_ISR_Flash( _isr_cookie ) \
- do{ \
- _CPU_ISR_Enable( _isr_cookie ); \
- _CPU_ISR_Disable( _isr_cookie ); \
- }while(0)
-
-/*
- * Map interrupt level in task mode onto the hardware that the CPU
- * actually provides. Currently, interrupt levels which do not
- * map onto the CPU in a generic fashion are undefined. Someday,
- * it would be nice if these were "mapped" by the application
- * via a callout. For example, m68k has 8 levels 0 - 7, levels
- * 8 - 255 would be available for bsp/application specific meaning.
- * This could be used to manage a programmable interrupt controller
- * via the rtems_task_mode directive.
- */
-
-#define _CPU_ISR_Set_level( new_level ) \
- do{ \
- if ( new_level ) a29k_disable_all(); \
- else a29k_enable_all(); \
- }while(0);
-
-/* end of ISR handler macros */
-
-/* Context handler macros */
-
-extern void _CPU_Context_save(
- Context_Control *new_context
-);
-
-/*
- * Initialize the context to a state suitable for starting a
- * task after a context restore operation. Generally, this
- * involves:
- *
- * - setting a starting address
- * - preparing the stack
- * - preparing the stack and frame pointers
- * - setting the proper interrupt level in the context
- * - initializing the floating point context
- *
- * This routine generally does not set any unnecessary register
- * in the context. The state of the "general data" registers is
- * undefined at task start time.
- *
- * NOTE: This is_fp parameter is TRUE if the thread is to be a floating
- * point thread. This is typically only used on CPUs where the
- * FPU may be easily disabled by software such as on the SPARC
- * where the PSR contains an enable FPU bit.
- */
-
-#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
- _isr, _entry_point, _is_fp ) \
- do{ /* allocate 1/4 of stack for memory stack, 3/4 of stack for register stack */ \
- unsigned32 _mem_stack_tmp = (unsigned32)(_stack_base) + (_size); \
- unsigned32 _reg_stack_tmp = (unsigned32)(_stack_base) + (((_size)*3)/4); \
- _mem_stack_tmp &= ~(CPU_ALIGNMENT-1); \
- _reg_stack_tmp &= ~(CPU_ALIGNMENT-1); \
- _CPU_Context_save(_the_context); \
- (_the_context)->msp = _mem_stack_tmp; /* gr125 */ \
- (_the_context)->lr1 = \
- (_the_context)->locals[1] = \
- (_the_context)->rfb = _reg_stack_tmp; /* gr127 */ \
- (_the_context)->gr1 = _reg_stack_tmp - 4 * 4; \
- (_the_context)->rab = _reg_stack_tmp - 128 * 4; /* gr126 */ \
- (_the_context)->local_count = 1-1; \
- (_the_context)->PC1 = _entry_point; \
- (_the_context)->PC0 = (unsigned32)((char *)_entry_point + 4); \
- if (_isr) { (_the_context)->OPS |= (TD | DI); } \
- else \
- { (_the_context)->OPS &= ~(TD | DI); } \
- }while(0)
-
-/*
- * This routine is responsible for somehow restarting the currently
- * executing task. If you are lucky, then all that is necessary
- * is restoring the context. Otherwise, there will need to be
- * a special assembly routine which does something special in this
- * case. Context_Restore should work most of the time. It will
- * not work if restarting self conflicts with the stack frame
- * assumptions of restoring a context.
- */
-
-#define _CPU_Context_Restart_self( _the_context ) \
- _CPU_Context_restore( (_the_context) )
-
-/*
- * The purpose of this macro is to allow the initial pointer into
- * a floating point context area (used to save the floating point
- * context) to be at an arbitrary place in the floating point
- * context area.
- *
- * This is necessary because some FP units are designed to have
- * their context saved as a stack which grows into lower addresses.
- * Other FP units can be saved by simply moving registers into offsets
- * from the base of the context area. Finally some FP units provide
- * a "dump context" instruction which could fill in from high to low
- * or low to high based on the whim of the CPU designers.
- */
-
-#define _CPU_Context_Fp_start( _base, _offset ) \
- ( (char *) (_base) + (_offset) )
-
-/*
- * This routine initializes the FP context area passed to it to.
- * There are a few standard ways in which to initialize the
- * floating point context. The code included for this macro assumes
- * that this is a CPU in which a "initial" FP context was saved into
- * _CPU_Null_fp_context and it simply copies it to the destination
- * context passed to it.
- *
- * Other models include (1) not doing anything, and (2) putting
- * a "null FP status word" in the correct place in the FP context.
- */
-
-#define _CPU_Context_Initialize_fp( _destination ) \
- do { \
- *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
- } while(0)
-
-/* end of Context handler macros */
-
-/* Fatal Error manager macros */
-
-/*
- * This routine copies _error into a known place -- typically a stack
- * location or a register, optionally disables interrupts, and
- * halts/stops the CPU.
- */
-
-#define _CPU_Fatal_halt( _error ) \
- a29k_fatal_error(_error)
-
-/* end of Fatal Error manager macros */
-
-/* Bitfield handler macros */
-
-/*
- * This routine sets _output to the bit number of the first bit
- * set in _value. _value is of CPU dependent type Priority_Bit_map_control.
- * This type may be either 16 or 32 bits wide although only the 16
- * least significant bits will be used.
- *
- * There are a number of variables in using a "find first bit" type
- * instruction.
- *
- * (1) What happens when run on a value of zero?
- * (2) Bits may be numbered from MSB to LSB or vice-versa.
- * (3) The numbering may be zero or one based.
- * (4) The "find first bit" instruction may search from MSB or LSB.
- *
- * RTEMS guarantees that (1) will never happen so it is not a concern.
- * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
- * _CPU_Priority_bits_index(). These three form a set of routines
- * which must logically operate together. Bits in the _value are
- * set and cleared based on masks built by _CPU_Priority_mask().
- * The basic major and minor values calculated by _Priority_Major()
- * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
- * to properly range between the values returned by the "find first bit"
- * instruction. This makes it possible for _Priority_Get_highest() to
- * calculate the major and directly index into the minor table.
- * This mapping is necessary to ensure that 0 (a high priority major/minor)
- * is the first bit found.
- *
- * This entire "find first bit" and mapping process depends heavily
- * on the manner in which a priority is broken into a major and minor
- * components with the major being the 4 MSB of a priority and minor
- * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
- * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
- * to the lowest priority.
- *
- * If your CPU does not have a "find first bit" instruction, then
- * there are ways to make do without it. Here are a handful of ways
- * to implement this in software:
- *
- * - a series of 16 bit test instructions
- * - a "binary search using if's"
- * - _number = 0
- * if _value > 0x00ff
- * _value >>=8
- * _number = 8;
- *
- * if _value > 0x0000f
- * _value >=8
- * _number += 4
- *
- * _number += bit_set_table[ _value ]
- *
- * where bit_set_table[ 16 ] has values which indicate the first
- * bit set
- */
-
-#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
-#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
-
-#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
-
-#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
- { \
- (_output) = 0; /* do something to prevent warnings */ \
- }
-
-#endif
-
-/* end of Bitfield handler macros */
-
-/*
- * This routine builds the mask which corresponds to the bit fields
- * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion
- * for that routine.
- */
-
-#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
-
-#define _CPU_Priority_Mask( _bit_number ) \
- ( 1 << (_bit_number) )
-
-#endif
-
-/*
- * This routine translates the bit numbers returned by
- * _CPU_Bitfield_Find_first_bit() into something suitable for use as
- * a major or minor component of a priority. See the discussion
- * for that routine.
- */
-
-#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
-
-#define _CPU_Priority_bits_index( _priority ) \
- (_priority)
-
-#endif
-
-/* end of Priority handler macros */
-
-/* functions */
-
-/*
- * _CPU_Initialize
- *
- * This routine performs CPU dependent initialization.
- */
-
-void _CPU_Initialize(
- rtems_cpu_table *cpu_table,
- void (*thread_dispatch)()
-);
-
-/*
- * _CPU_ISR_install_raw_handler
- *
- * This routine installs a "raw" interrupt handler directly into the
- * processor's vector table.
- */
-
-void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-);
-
-/*
- * _CPU_ISR_install_vector
- *
- * This routine installs an interrupt vector.
- */
-
-void _CPU_ISR_install_vector(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-);
-
-/*
- * _CPU_Install_interrupt_stack
- *
- * This routine installs the hardware interrupt stack pointer.
- *
- * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
- * is TRUE.
- */
-
-void _CPU_Install_interrupt_stack( void );
-
-/*
- * _CPU_Thread_Idle_body
- *
- * This routine is the CPU dependent IDLE thread body.
- *
- * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
- * is TRUE.
- */
-
-void _CPU_Thread_Idle_body( void );
-
-/*
- * _CPU_Context_switch
- *
- * This routine switches from the run context to the heir context.
- */
-
-void _CPU_Context_switch(
- Context_Control *run,
- Context_Control *heir
-);
-
-/*
- * _CPU_Context_restore
- *
- * This routine is generally used only to restart self in an
- * efficient manner. It may simply be a label in _CPU_Context_switch.
- *
- * NOTE: May be unnecessary to reload some registers.
- */
-
-void _CPU_Context_restore(
- Context_Control *new_context
-);
-
-/*
- * _CPU_Context_save_fp
- *
- * This routine saves the floating point context passed to it.
- */
-
-void _CPU_Context_save_fp(
- void **fp_context_ptr
-);
-
-/*
- * _CPU_Context_restore_fp
- *
- * This routine restores the floating point context passed to it.
- */
-
-void _CPU_Context_restore_fp(
- void **fp_context_ptr
-);
-
-/* The following routine swaps the endian format of an unsigned int.
- * It must be static because it is referenced indirectly.
- *
- * This version will work on any processor, but if there is a better
- * way for your CPU PLEASE use it. The most common way to do this is to:
- *
- * swap least significant two bytes with 16-bit rotate
- * swap upper and lower 16-bits
- * swap most significant two bytes with 16-bit rotate
- *
- * Some CPUs have special instructions which swap a 32-bit quantity in
- * a single instruction (e.g. i486). It is probably best to avoid
- * an "endian swapping control bit" in the CPU. One good reason is
- * that interrupts would probably have to be disabled to insure that
- * an interrupt does not try to access the same "chunk" with the wrong
- * endian. Another good reason is that on some CPUs, the endian bit
- * endianness for ALL fetches -- both code and data -- so the code
- * will be fetched incorrectly.
- */
-
-#define CPU_swap_u32( value ) \
- ((value&0xff) << 24) | (((value >> 8)&0xff) << 16) | \
- (((value >> 16)&0xff) << 8) | ((value>>24)&0xff)
-
-#define CPU_swap_u16( value ) \
- (((value&0xff) << 8) | ((value >> 8)&0xff))
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/cpukit/score/cpu/a29k/rtems/score/cpu_asm.h b/cpukit/score/cpu/a29k/rtems/score/cpu_asm.h
deleted file mode 100644
index d2c09fa103..0000000000
--- a/cpukit/score/cpu/a29k/rtems/score/cpu_asm.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * cpu_asm.h
- *
- * Very loose template for an include file for the cpu_asm.? file
- * if it is implemented as a ".S" file (preprocessed by cpp) instead
- * of a ".s" file (preprocessed by gm4 or gasp).
- *
- * COPYRIGHT (c) 1989-1999.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- *
- */
-/* @(#)cpu_asm.h 06/08/96 1.2 */
-
-#ifndef __CPU_ASM_h
-#define __CPU_ASM_h
-
-/* pull in the generated offsets */
-
-/* #include <rtems/score/offsets.h> */
-
-/*
- * Hardware General Registers
- */
-
-/* put something here */
-
-/*
- * Hardware Floating Point Registers
- */
-
-/* put something here */
-
-/*
- * Hardware Control Registers
- */
-
-/* put something here */
-
-/*
- * Calling Convention
- */
-
-/* put something here */
-
-/*
- * Temporary registers
- */
-
-/* put something here */
-
-/*
- * Floating Point Registers - SW Conventions
- */
-
-/* put something here */
-
-/*
- * Temporary floating point registers
- */
-
-/* put something here */
-
-#endif
-
-/* end of file */
diff --git a/cpukit/score/cpu/a29k/rtems/score/types.h b/cpukit/score/cpu/a29k/rtems/score/types.h
deleted file mode 100644
index 130fd30dd4..0000000000
--- a/cpukit/score/cpu/a29k/rtems/score/types.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* no_cputypes.h
- *
- * This include file contains type definitions pertaining to the Intel
- * no_cpu processor family.
- *
- * COPYRIGHT (c) 1989-1999.
- * On-Line Applications Research Corporation (OAR).
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-
-#ifndef __NO_CPU_TYPES_h
-#define __NO_CPU_TYPES_h
-
-#ifndef ASM
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * This section defines the basic types for this processor.
- */
-
-typedef unsigned char unsigned8; /* unsigned 8-bit integer */
-typedef unsigned short unsigned16; /* unsigned 16-bit integer */
-typedef unsigned int unsigned32; /* unsigned 32-bit integer */
-typedef unsigned long unsigned64; /* unsigned 64-bit integer */
-
-typedef unsigned16 Priority_Bit_map_control;
-
-typedef signed char signed8; /* 8-bit signed integer */
-typedef signed short signed16; /* 16-bit signed integer */
-typedef signed int signed32; /* 32-bit signed integer */
-typedef signed long signed64; /* 64 bit signed integer */
-
-typedef unsigned32 boolean; /* Boolean value */
-
-typedef float single_precision; /* single precision float */
-typedef double double_precision; /* double precision float */
-
-typedef void no_cpu_isr;
-typedef void ( *no_cpu_isr_entry )( void );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !ASM */
-
-#endif
-/* end of include file */
diff --git a/cpukit/score/cpu/a29k/sig.S b/cpukit/score/cpu/a29k/sig.S
deleted file mode 100644
index 9caddf1382..0000000000
--- a/cpukit/score/cpu/a29k/sig.S
+++ /dev/null
@@ -1,213 +0,0 @@
-;/*
-; * $Id$
-; */
-
-; .include "register.ah"
-#include <amd.ah>
-#include <pswmacro.ah>
- .comm WindowSize,4
- .text
- .reg it0,gr64
- .reg it1,gr65
- .reg it2,gr66
- .reg it3,gr67
- .reg v0,gr96
- .reg v1,gr97
- .reg v2,gr98
- .reg v3,gr99
- .reg trapreg,it0
- .reg FPStat0,gr79
- .reg FPStat1,gr79
- .reg FPStat2,gr79
- .reg FPStat3,gr79
-
- .global _intr14
-_intr14:
-#if 0
- const it3,14
- sup_sv
- jmp interrupt
- nop
-#endif
-
- .global _intr18
-_intr18:
-#if 0
- const it3,18
- sup_sv
- jmp interrupt
- nop
-#endif
-
- .global _intr19
-_intr19:
-#if 0
- const it3,19
- sup_sv
- jmp interrupt
- nop
-#endif
-
-interrupt:
-#if 0
- push msp,it3
- push msp,gr1
- push msp,rab
- const it0,512
- sub rab,rfb,it0 ;set rab = rfb-512
- pushsr msp,it0,pc0
- pushsr msp,it0,pc1
- pushsr msp,it0,pc2
- pushsr msp,it0,cha
- pushsr msp,it0,chd
- pushsr msp,it0,chc
- pushsr msp,it0,alu
- pushsr msp,it0,ops
- push msp,tav
-;
-;now come off freeze, and go to user-mode code.
-;ensure load/store does not restart
-;
- mtsrim chc,0
-
- mfsr it0, cps
- const it1, FZ
- consth it1, FZ
- andn it0, it0, it1
- const it1,(DI|TD)
- consth it1,(DI|TD)
- or it0,it1,it0
- mtsr cps, it0
-; fall through to _sigcode
-#endif
-
- .extern _a29k_ISR_Handler
- .global _sigcode
-_sigcode:
-#if 0
-
- push msp, lr1 ; R stack support
- push msp, rfb ; support
- push msp, msp ; M stack support
-
-; push msp, FPStat0 ; Floating point 0
-; push msp, FPStat1 ; Floating point 1
-; push msp, FPStat2 ; Floating point 2
-; push msp, FPStat3 ; Floating point 3
- sub msp,msp,4*4
-
- pushsr msp, tav, IPA ; save user mode special
- pushsr msp, tav, IPB ; save user mode special
- pushsr msp, tav, IPC ; save user mode special
- pushsr msp, tav, Q ; save user mode special
-
- sub msp, msp, 29*4 ; gr96-gr124
- mtsrim cr, 29-1 ;
- storem 0, 0, gr96, msp ;
-
-
- const v0, WindowSize ; Window Size value
- consth v0, WindowSize ; Window Size value
- load 0, 0, v0, v0 ; load Window size
- add v2, msp, SIGCTX_RAB ; intr RAB value
-
- load 0, 0, v2, v2 ; rab value
-
- sub v1, rfb, v2 ;
- cpgeu v1, v1, v0 ;
- jmpt v1, nfill ; jmp if spill
- add v1, gr1, 8 ;
-
- cpgtu v1, v1, rfb ; longjump test
- jmpt v1, nfill ;
- nop ;
-
-ifill:
- add v0, msp, SIGCTX_RAB+4 ;
- push v0, rab ;
- const v2, fill+4 ;
- consth v2, fill+4 ;
-
- push v0, v2 ; resave PC0
- sub v2, v2, 4 ;
- push v0, v2 ; resave PC1
- const v2, 0 ;
-
- sub v0, v0, 3*4 ;
- push v0, v2 ;
-
-nfill:
- cpgtu v0, gr1, rfb ; if gr1>rfb -> gr1=rfb
- jmpt v0, lower ;
- cpltu v0, gr1, rab ;
- jmpt v0, raise ; gr1<rab then gr1=rab
- nop ;
-
-sendsig:
- sub gr1, gr1, RALLOC ;
- asgeu V_SPILL, gr1, rab ;
- add lr1, rfb, 0 ;
- add v1, msp, SIGCTX_SIG ;
-
-cont:
- add lr2,it3,0 ; signal #
- call lr0, _a29k_ISR_Handler ; call the handler
- nop
-
- nop ; WASTE
- jmp _a29k_sigdfl ; return code
- nop ; WASTE
- nop ; ALIGN
-
-lower:
- jmp sendsig ;
- add gr1, rfb, 0 ;
-raise:
- jmp sendsig ;
- add gr1, rab, 0 ;
-#endif
-
-
- .global _a29k_sigdfl_sup
-_a29k_sigdfl_sup:
-#if 0
- repair_R_stack ;
- repair_regs ;
- sig_return ; return
- halt ; never executes
-#endif
-
-
- .global _sigret
-_sigret:
-#if 0
-;assume msp points to tav
- mfsr it0,cps
- const it1,FZ
- or it1,it0,it1
- mtsr cps,it1
- nop
- nop
-_sigret1:
- pop tav,msp
- popsr ops,it0,msp
- popsr alu,it0,msp
- popsr chc,it0,msp
- popsr chd,it0,msp
- popsr cha,it0,msp
- popsr pc2,it0,msp
- popsr pc1,it0,msp
- popsr pc0,it0,msp
- pop rab,msp
- pop it0,msp
- add gr1,it0,0
- add msp,msp,4 ;discount signal
- iret
-#endif
-
-_a29k_sigdfl:
-#if 0
- asneq SIGDFL,gr1,gr1
- jmpi lr0
- nop
-#endif
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