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authorJoel Sherrill <joel.sherrill@OARcorp.com>2003-09-26 21:35:21 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2003-09-26 21:35:21 +0000
commit024fd916dca3613588dbe4230d913713e45ef7cc (patch)
treeec14cb08ab318cfa4d2ff973afe80f3283de6bbd
parent2003-09-26 Joel Sherrill <joel@OARcorp.com> (diff)
downloadrtems-024fd916dca3613588dbe4230d913713e45ef7cc.tar.bz2
2003-09-26 Joel Sherrill <joel@OARcorp.com>
* cpu/hppa1.1/.cvsignore, cpu/hppa1.1/ChangeLog, cpu/hppa1.1/Makefile.am, cpu/hppa1.1/configure.ac, cpu/hppa1.1/cpu.c, cpu/hppa1.1/cpu_asm.S, cpu/hppa1.1/rtems/.cvsignore, cpu/hppa1.1/rtems/score/.cvsignore, cpu/hppa1.1/rtems/score/cpu.h, cpu/hppa1.1/rtems/score/cpu_asm.h, cpu/hppa1.1/rtems/score/hppa.h, cpu/hppa1.1/rtems/score/types.h: Removed.
Diffstat
-rw-r--r--cpukit/score/ChangeLog9
-rw-r--r--cpukit/score/cpu/hppa1.1/.cvsignore14
-rw-r--r--cpukit/score/cpu/hppa1.1/ChangeLog165
-rw-r--r--cpukit/score/cpu/hppa1.1/Makefile.am62
-rw-r--r--cpukit/score/cpu/hppa1.1/configure.ac29
-rw-r--r--cpukit/score/cpu/hppa1.1/cpu.c184
-rw-r--r--cpukit/score/cpu/hppa1.1/cpu_asm.S805
-rw-r--r--cpukit/score/cpu/hppa1.1/rtems/.cvsignore2
-rw-r--r--cpukit/score/cpu/hppa1.1/rtems/score/.cvsignore2
-rw-r--r--cpukit/score/cpu/hppa1.1/rtems/score/cpu.h653
-rw-r--r--cpukit/score/cpu/hppa1.1/rtems/score/cpu_asm.h73
-rw-r--r--cpukit/score/cpu/hppa1.1/rtems/score/hppa.h727
-rw-r--r--cpukit/score/cpu/hppa1.1/rtems/score/types.h46
13 files changed, 9 insertions, 2762 deletions
diff --git a/cpukit/score/ChangeLog b/cpukit/score/ChangeLog
index a7528ffd72..a1f8857619 100644
--- a/cpukit/score/ChangeLog
+++ b/cpukit/score/ChangeLog
@@ -1,3 +1,12 @@
+2003-09-26 Joel Sherrill <joel@OARcorp.com>
+
+ * cpu/hppa1.1/.cvsignore, cpu/hppa1.1/ChangeLog,
+ cpu/hppa1.1/Makefile.am, cpu/hppa1.1/configure.ac, cpu/hppa1.1/cpu.c,
+ cpu/hppa1.1/cpu_asm.S, cpu/hppa1.1/rtems/.cvsignore,
+ cpu/hppa1.1/rtems/score/.cvsignore, cpu/hppa1.1/rtems/score/cpu.h,
+ cpu/hppa1.1/rtems/score/cpu_asm.h, cpu/hppa1.1/rtems/score/hppa.h,
+ cpu/hppa1.1/rtems/score/types.h: Removed.
+
2003-09-15 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
PR 489/rtems
diff --git a/cpukit/score/cpu/hppa1.1/.cvsignore b/cpukit/score/cpu/hppa1.1/.cvsignore
deleted file mode 100644
index bfdfd995be..0000000000
--- a/cpukit/score/cpu/hppa1.1/.cvsignore
+++ /dev/null
@@ -1,14 +0,0 @@
-aclocal.m4
-autom4te*.cache
-config.cache
-config.guess
-config.log
-config.status
-config.sub
-configure
-depcomp
-install-sh
-Makefile
-Makefile.in
-missing
-mkinstalldirs
diff --git a/cpukit/score/cpu/hppa1.1/ChangeLog b/cpukit/score/cpu/hppa1.1/ChangeLog
deleted file mode 100644
index 049cc914ea..0000000000
--- a/cpukit/score/cpu/hppa1.1/ChangeLog
+++ /dev/null
@@ -1,165 +0,0 @@
-2003-09-04 Joel Sherrill <joel@OARcorp.com>
-
- * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/hppa.h: URL for
- license changed.
-
-2003-08-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
-
-2003-03-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Remove AC_CONFIG_AUX_DIR.
-
-2002-12-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Require autoconf-2.57 + automake-1.7.2.
- * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
-
-2002-11-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Fix package name.
-
-2002-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
-
-2002-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * .cvsignore: Reformat.
- Add autom4te*cache.
- Remove autom4te.cache.
-
-2002-07-26 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Build libscorecpu.a instead of rtems-cpu.rel.
-
-2002-07-22 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Use .$(OBJEXT) instead of .o.
-
-2002-07-22 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Use . instead of .o.
-
-2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: RTEMS_TOP(../../../..).
-
-2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * rtems.S: Remove.
- * Makefile.am: Reflect changes above.
-
-2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Remove RTEMS_PROJECT_ROOT.
-
-2002-06-27 Joel Sherrill <joel@OARcorp.com>
-
- * Makefile.am, cpu.c, cpu_asm.S, rtems.S: Modified to make
- this all compile again. It has been a while since we have
- had a semi-working hppa1.1-rtems cross compiler. :)
-
-2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Add RTEMS_PROG_CCAS
-
-2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
- Add AC_PROG_RANLIB.
-
-2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
- Use ../../../aclocal.
-
-2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * rtems/score/hppa.h: Remove rtems/score/targopts.h.
-
-2001-04-03 Joel Sherrill <joel@OARcorp.com>
-
- * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
- * rtems/score/hppa1.1types.h: Removed.
- * rtems/score/types.h: New file via CVS magic.
- * Makefile.am, rtems/score/cpu.h: Account for name change.
-
-2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * configure.ac:
- AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
- AM_INIT_AUTOMAKE([no-define foreign 1.6]).
- * Makefile.am: Remove AUTOMAKE_OPTIONS.
-
-2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * rtems/Makefile.am: Removed.
- * rtems/score/Makefile.am: Removed.
- * configure.ac: Reflect changes above.
- * Makefile.am: Reflect changes above.
-
-2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Add multilib support.
-
-2001-11-28 Joel Sherrill <joel@OARcorp.com>,
-
- This was tracked as PR91.
- * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
- is used to specify if the port uses the standard macro for this (FALSE).
- A TRUE setting indicates the port provides its own implementation.
-
-2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * .cvsignore: Add autom4te.cache for autoconf > 2.52.
- * configure.in: Remove.
- * configure.ac: New file, generated from configure.in by autoupdate.
-
-2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * rtems/score/Makefile.am: Use 'CLEANFILES ='.
- * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
-
-2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Remove references to PROJECT_INCLUDE.
- * rtems/score/Makefile.am:
- Apply include_*HEADERS instead of H_FILES.
-
-2001-01-03 Joel Sherrill <joel@OARcorp.com>
-
- * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
- * cpu_asm.S: Modify to properly dereference _ISR_Vector_table
- now that it is dynamically allocated.
-
-2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
-
-2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
-
-2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
- Switch to GNU canonicalization.
-
-2000-09-25 Joel Sherrill <joel@OARcorp.com>
-
- * rtems/score/hppa.h: Switched to using cpuopts.h not
- targopts.h to reduce dependency on BSP.
-
-2000-09-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * rtems/score/Makefile.am: Use PROJECT_TOPdir in path to genoffsets.
-
-2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
-
- * Makefile.am: Include compile.am.
-
-2000-08-10 Joel Sherrill <joel@OARcorp.com>
-
- * ChangeLog: New file.
diff --git a/cpukit/score/cpu/hppa1.1/Makefile.am b/cpukit/score/cpu/hppa1.1/Makefile.am
deleted file mode 100644
index 920e5501e0..0000000000
--- a/cpukit/score/cpu/hppa1.1/Makefile.am
+++ /dev/null
@@ -1,62 +0,0 @@
-##
-## $Id$
-##
-
-ACLOCAL_AMFLAGS = -I ../../../aclocal
-
-include $(top_srcdir)/../../../automake/multilib.am
-include $(top_srcdir)/../../../automake/compile.am
-include $(top_srcdir)/../../../automake/lib.am
-
-$(PROJECT_INCLUDE)/%.h: %.h
- $(INSTALL_DATA) $< $@
-
-$(PROJECT_INCLUDE):
- $(mkinstalldirs) $@
-
-$(PROJECT_INCLUDE)/rtems:
- $(mkinstalldirs) $@
-
-$(PROJECT_INCLUDE)/rtems/score:
- $(mkinstalldirs) $@
-
-include_HEADERS=
-PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%)
-
-include_rtems_scoredir = $(includedir)/rtems/score
-include_rtems_score_HEADERS = \
- rtems/score/cpu.h \
- rtems/score/cpu_asm.h \
- rtems/score/hppa.h \
- rtems/score/types.h \
- rtems/score/offsets.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \
- $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h)
-
-C_FILES = cpu.c
-OBJS = $(C_FILES:%.c=$(ARCH)/%.$(OBJEXT))
-
-S_FILES = cpu_asm.S
-OBJS += $(S_FILES:%.S=$(ARCH)/%.$(OBJEXT))
-
-LIB = $(ARCH)/libscorecpu.a
-
-$(LIB): $(OBJS)
- $(make-library)
-
-all-local: $(ARCH) rtems/score/offsets.h $(PREINSTALL_FILES) $(LIB) \
- $(TMPINSTALL_FILES)
-
-EXTRA_DIST = cpu.c cpu_asm.S
-
-# FIXME: We should get rid of genoffsets
-GENOFFSETS = $(PROJECT_TOPdir)/tools/cpu/hppa1.1/genoffsets
-
-GENERIC_H_FILES = rtems/score/offsets.h
-rtems/score/offsets.h: $(GENOFFSETS) rtems/score/cpu.h
- $(mkinstalldirs) rtems/score
- $(RM) $@
- $(GENOFFSETS) > $@
-CLEANFILES = rtems/score/offsets.h
-
-include $(top_srcdir)/../../../automake/local.am
diff --git a/cpukit/score/cpu/hppa1.1/configure.ac b/cpukit/score/cpu/hppa1.1/configure.ac
deleted file mode 100644
index b97dec5353..0000000000
--- a/cpukit/score/cpu/hppa1.1/configure.ac
+++ /dev/null
@@ -1,29 +0,0 @@
-## Process this file with autoconf to produce a configure script.
-##
-## $Id$
-
-AC_PREREQ(2.57)
-AC_INIT([rtems-cpukit-score-cpu-hppa1.1],[_RTEMS_VERSION],[rtems-bugs@rtems.com])
-AC_CONFIG_SRCDIR([cpu_asm.S])
-RTEMS_TOP(../../../..)
-
-RTEMS_CANONICAL_TARGET_CPU
-
-AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.7.2])
-AM_MAINTAINER_MODE
-
-RTEMS_ENV_RTEMSCPU
-
-RTEMS_CHECK_CPU
-RTEMS_CANONICAL_HOST
-
-RTEMS_PROG_CC_FOR_TARGET
-RTEMS_PROG_CCAS
-RTEMS_CANONICALIZE_TOOLS
-AC_PROG_RANLIB
-
-RTEMS_CHECK_NEWLIB
-
-# Explicitly list all Makefiles here
-AC_CONFIG_FILES([Makefile])
-AC_OUTPUT
diff --git a/cpukit/score/cpu/hppa1.1/cpu.c b/cpukit/score/cpu/hppa1.1/cpu.c
deleted file mode 100644
index 84f0e90188..0000000000
--- a/cpukit/score/cpu/hppa1.1/cpu.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * HP PA-RISC Dependent Source
- *
- * COPYRIGHT (c) 1994 by Division Incorporated
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.com/license/LICENSE.
- *
- * $Id$
- */
-
-#include <rtems/system.h>
-#include <rtems/score/isr.h>
-void hppa_cpu_halt(unsigned32 the_error);
-
-
-/*PAGE
- *
- * _CPU_ISR_install_raw_handler
- */
-
-void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-)
-{
- /*
- * This is unsupported. For HPPA this function is handled by BSP
- */
-
- _CPU_Fatal_halt( 0xdeaddead );
-}
-
-
-
-/*
- * This is the default handler which is called if
- * _CPU_ISR_install_vector() has not been called for the
- * specified vector. It simply forwards onto the spurious
- * handler defined in the cpu-table.
- */
-
-static ISR_Handler
-hppa_interrupt_report_spurious(ISR_Vector_number vector,
- void* rtems_isr_frame) /* HPPA extension */
-{
-
- /*
- * If the CPU table defines a spurious_handler, then
- * call it. If the handler returns halt.
- */
- if ( _CPU_Table.spurious_handler )
- _CPU_Table.spurious_handler(vector, rtems_isr_frame);
-
- hppa_cpu_halt(vector);
-}
-
-
-/*PAGE
- *
- * _CPU_ISR_Get_level
- */
-
-unsigned32 _CPU_ISR_Get_level(void)
-{
- int level;
- HPPA_ASM_SSM(0, level); /* change no bits; just get copy */
- if (level & HPPA_PSW_I)
- return 0;
- return 1;
-}
-
-/*PAGE
- *
- * _CPU_ISR_install_vector
- *
- * This kernel routine installs the RTEMS handler for the
- * specified vector. The handler is a C callable routine.
- *
- * Input parameters:
- * vector - interrupt vector number
- * old_handler - former ISR for this vector number
- * new_handler - replacement ISR for this vector number
- *
- * Output parameters: NONE
- *
- */
-
-void _CPU_ISR_install_vector(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-)
-{
- *old_handler = _ISR_Vector_table[vector];
-
- _ISR_Vector_table[vector] = new_handler;
-}
-
-/* _CPU_Initialize
- *
- * This routine performs processor dependent initialization.
- *
- * INPUT PARAMETERS:
- * cpu_table - CPU table to initialize
- * thread_dispatch - address of disptaching routine
- *
- */
-
-void _CPU_Initialize(
- rtems_cpu_table *cpu_table,
- void (*thread_dispatch) /* ignored on this CPU */
-)
-{
- register unsigned8 *fp_context;
- unsigned32 i;
- proc_ptr old_handler;
-
- /*
- * This is the default fp context for all tasks
- * Set it up so that denormalized results go to zero.
- */
-
- fp_context = (unsigned8*) &_CPU_Null_fp_context;
- for (i=0 ; i<sizeof(Context_Control_fp); i++)
- *fp_context++ = 0;
- *((unsigned32 *) &_CPU_Null_fp_context) = HPPA_FPSTATUS_D;
-
- /*
- * Save r27 into _CPU_Default_gr27 so it will hopefully be the correct
- * global data pointer for the entire system.
- */
-
- asm volatile( "stw %%r27,%0" : "=m" (_CPU_Default_gr27): );
-
- /*
- * Init the 2nd level interrupt handlers
- */
-
- for (i=0; i < CPU_INTERRUPT_NUMBER_OF_VECTORS; i++)
- _CPU_ISR_install_vector(i,
- hppa_interrupt_report_spurious,
- &old_handler);
-
- _CPU_Table = *cpu_table;
-
-}
-
-
-/*
- * Halt the system.
- * Called by the _CPU_Fatal_halt macro
- *
- * XXX
- * Later on, this will allow us to return to the prom.
- * For now, we just ignore 'type_of_halt'
- *
- * XXX
- * NOTE: for gcc, this function must be at the bottom
- * of the file, that is because if it is at the top
- * of the file, gcc will inline it's calls. Since
- * the function uses the HPPA_ASM_LABEL() macro, when
- * gcc inlines it, you get two definitions of the same
- * label name, which is an assembly error.
- */
-
-
-void
-hppa_cpu_halt(unsigned32 the_error)
-{
- unsigned32 isrlevel;
-
- _CPU_ISR_Disable(isrlevel);
-
- /*
- * XXXXX NOTE: This label is only needed that that when
- * the simulator stops, it shows the label name specified
- */
- /* HPPA_ASM_LABEL("_asm_hppa_cpu_halt");*/
- HPPA_ASM_BREAK(0, 0);
-}
-
diff --git a/cpukit/score/cpu/hppa1.1/cpu_asm.S b/cpukit/score/cpu/hppa1.1/cpu_asm.S
deleted file mode 100644
index 214fb36b65..0000000000
--- a/cpukit/score/cpu/hppa1.1/cpu_asm.S
+++ /dev/null
@@ -1,805 +0,0 @@
-/*
- * TODO:
- * Context_switch needs to only save callee save registers
- * I think this means can skip: r1, r2, r19-29, r31
- * Ref: p 3-2 of Procedure Calling Conventions Manual
- * This should be #ifndef DEBUG so that debugger has
- * accurate visibility into all registers
- *
- * This file contains the assembly code for the HPPA implementation
- * of RTEMS.
- *
- * COPYRIGHT (c) 1994,95 by Division Incorporated
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.com/license/LICENSE.
- *
- * $Id$
- */
-
-#include <rtems/score/hppa.h>
-#include <rtems/score/cpu_asm.h>
-#include <rtems/score/cpu.h>
-#include <rtems/score/offsets.h>
-
-#if 0
-#define TEXT_SEGMENT \
- .SPACE $TEXT$ !\
- .SUBSPA $CODE$
-#define RO_SEGMENT \
- .SPACE $TEXT$ !\
- .SUBSPA $lit$
-#define DATA_SEGMENT \
- .SPACE $PRIVATE$ !\
- .SUBSPA $data$
-#define BSS_SEGMENT \
- .SPACE $PRIVATE$ !\
- .SUBSPA $bss$
-#else
-#define TEXT_SEGMENT .text
-#define RO_SEGMENT .rodata
-#define DATA_SEGMENT .data
-#define BSS_SEGMENT .bss
-#endif
-
-
-
-#if 0
- .SPACE $PRIVATE$
- .SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31
- .SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82
- .SPACE $TEXT$
- .SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44
- .SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY
- .SPACE $TEXT$
- .SUBSPA $CODE$
-
-#endif
- TEXT_SEGMENT
-
-/*
- * Special register usage for context switch and interrupts
- * Stay away from %cr28 which is used for TLB misses on 72000
- */
-
-isr_arg0 .reg %cr24
-isr_r9 .reg %cr25
-isr_r8 .reg %cr26
-
-/*
- * Interrupt stack frame looks like this
- *
- * offset item
- * -----------------------------------------------------------------
- * INTEGER_CONTEXT_OFFSET Context_Control
- * FP_CONTEXT_OFFSET Context_Control_fp
- *
- * It is padded out to a multiple of 64
- */
-
-
-/*PAGE^L
- * void _Generic_ISR_Handler()
- *
- * This routine provides the RTEMS interrupt management.
- *
- * We jump here from the interrupt vector.
- * The HPPA hardware has done some stuff for us:
- * PSW saved in IPSW
- * PSW set to 0
- * PSW[E] set to default (0)
- * PSW[M] set to 1 iff this is HPMC
- *
- * IIA queue is frozen (since PSW[Q] is now 0)
- * privilege level promoted to 0
- * IIR, ISR, IOR potentially updated if PSW[Q] was 1 at trap
- * registers GR 1,8,9,16,17,24,25 copied to shadow regs
- * SHR 0 1 2 3 4 5 6
- *
- * Our vector stub (in the BSP) MUST have done the following:
- *
- * a) Saved the original %r9 into %isr_r9 (%cr25)
- * b) Placed the vector number in %r9
- * c) Was allowed to also destroy $isr_r8 (%cr26),
- * but the stub was NOT allowed to destroy any other registers.
- *
- * The typical stub sequence (in the BSP) should look like this:
- *
- * a) mtctl %r9,isr_r9 ; (save r9 in cr25)
- * b) ldi vector,%r9 ; (load constant vector number in r9)
- * c) mtctl %r8,isr_r8 ; (save r8 in cr26)
- * d) ldil L%MY_BSP_first_level_interrupt_handler,%r8
- * e) ldo R%MY_BSP_first_level_interrupt_handler(%r8),%r8
- * ; (point to BSP raw handler table)
- * f) ldwx,s %r9(%r8),%r8 ; (load value from raw handler table)
- * g) bv 0(%r8) ; (call raw handler: _Generic_ISR_Handler)
- * h) mfctl isr_r8,%r8 ; (restore r8 from cr26 in delay slot)
- *
- * Optionally, steps (c) thru (h) _could_ be replaced with a single
- * bl,n _Generic_ISR_Handler,%r0
- *
- *
- */
- .EXPORT _Generic_ISR_Handler,ENTRY,PRIV_LEV=0
-_Generic_ISR_Handler:
- .PROC
- .CALLINFO FRAME=0,NO_CALLS
- .ENTRY
-
- mtctl arg0, isr_arg0
-
-/*
- * save interrupt state
- */
- mfctl ipsw, arg0
- stw arg0, IPSW_OFFSET(sp)
-
- mfctl iir, arg0
- stw arg0, IIR_OFFSET(sp)
-
- mfctl ior, arg0
- stw arg0, IOR_OFFSET(sp)
-
- mfctl pcoq, arg0
- stw arg0, PCOQFRONT_OFFSET(sp)
-
- mtctl %r0, pcoq
- mfctl pcoq, arg0
- stw arg0, PCOQBACK_OFFSET(sp)
-
- mfctl %sar, arg0
- stw arg0, SAR_OFFSET(sp)
-
-/*
- * Build an interrupt frame to hold the contexts we will need.
- * We have already saved the interrupt items on the stack
- *
- * At this point the following registers are damaged wrt the interrupt
- * reg current value saved value
- * ------------------------------------------------
- * arg0 scratch isr_arg0 (cr24)
- * r9 vector number isr_r9 (cr25)
- *
- * Point to beginning of integer context and
- * save the integer context
- */
- stw %r1,R1_OFFSET(sp)
- stw %r2,R2_OFFSET(sp)
- stw %r3,R3_OFFSET(sp)
- stw %r4,R4_OFFSET(sp)
- stw %r5,R5_OFFSET(sp)
- stw %r6,R6_OFFSET(sp)
- stw %r7,R7_OFFSET(sp)
- stw %r8,R8_OFFSET(sp)
-/*
- * skip r9
- */
- stw %r10,R10_OFFSET(sp)
- stw %r11,R11_OFFSET(sp)
- stw %r12,R12_OFFSET(sp)
- stw %r13,R13_OFFSET(sp)
- stw %r14,R14_OFFSET(sp)
- stw %r15,R15_OFFSET(sp)
- stw %r16,R16_OFFSET(sp)
- stw %r17,R17_OFFSET(sp)
- stw %r18,R18_OFFSET(sp)
- stw %r19,R19_OFFSET(sp)
- stw %r20,R20_OFFSET(sp)
- stw %r21,R21_OFFSET(sp)
- stw %r22,R22_OFFSET(sp)
- stw %r23,R23_OFFSET(sp)
- stw %r24,R24_OFFSET(sp)
- stw %r25,R25_OFFSET(sp)
-/*
- * skip arg0
- */
- stw %r27,R27_OFFSET(sp)
- stw %r28,R28_OFFSET(sp)
- stw %r29,R29_OFFSET(sp)
- stw %r30,R30_OFFSET(sp)
- stw %r31,R31_OFFSET(sp)
-
-/* Now most registers are available since they have been saved
- *
- * The following items are currently wrong in the integer context
- * reg current value saved value
- * ------------------------------------------------
- * arg0 scratch isr_arg0 (cr24)
- * r9 vector number isr_r9 (cr25)
- *
- * Fix them
- */
-
- mfctl isr_arg0,%r3
- stw %r3,ARG0_OFFSET(sp)
-
- mfctl isr_r9,%r3
- stw %r3,R9_OFFSET(sp)
-
-/*
- * At this point we are done with isr_arg0, and isr_r9 control registers
- *
- * Prepare to re-enter virtual mode
- * We need Q in case the interrupt handler enables interrupts
- */
-
- ldil L%CPU_PSW_DEFAULT, arg0
- ldo R%CPU_PSW_DEFAULT(arg0), arg0
- mtctl arg0, ipsw
-
-/*
- * Now jump to "rest_of_isr_handler" with the rfi
- * We are assuming the space queues are all correct already
- */
-
- ldil L%rest_of_isr_handler, arg0
- ldo R%rest_of_isr_handler(arg0), arg0
- mtctl arg0, pcoq
- ldo 4(arg0), arg0
- mtctl arg0, pcoq
-
- rfi
- nop
-
-/*
- * At this point we are back in virtual mode and all our
- * normal addressing is once again ok.
- *
- * It is now ok to take an exception or trap
- */
-
-rest_of_isr_handler:
-
-/*
- * Point to beginning of float context and
- * save the floating point context -- doing whatever patches are necessary
- */
-
- .call ARGW0=GR
- bl _CPU_Save_float_context,%r2
- ldo FP_CONTEXT_OFFSET(sp),arg0
-
-/*
- * save the ptr to interrupt frame as an argument for the interrupt handler
- */
-
- copy sp, arg1
-
-/*
- * Advance the frame to point beyond all interrupt contexts (integer & float)
- * this also includes the pad to align to 64byte stack boundary
- */
- ldo CPU_INTERRUPT_FRAME_SIZE(sp), sp
-
-/*
- * r3 -- &_ISR_Nest_level
- * r5 -- value _ISR_Nest_level
- * r4 -- &_Thread_Dispatch_disable_level
- * r6 -- value _Thread_Dispatch_disable_level
- * r9 -- vector number
- */
-
- .import _ISR_Nest_level,data
- ldil L%_ISR_Nest_level,%r3
- ldo R%_ISR_Nest_level(%r3),%r3
- ldw 0(%r3),%r5
-
- .import _Thread_Dispatch_disable_level,data
- ldil L%_Thread_Dispatch_disable_level,%r4
- ldo R%_Thread_Dispatch_disable_level(%r4),%r4
- ldw 0(%r4),%r6
-
-/*
- * increment interrupt nest level counter. If outermost interrupt
- * switch the stack and squirrel away the previous sp.
- */
- addi 1,%r5,%r5
- stw %r5, 0(%r3)
-
-/*
- * compute and save new stack (with frame)
- * just in case we are nested -- simpler this way
- */
- comibf,= 1,%r5,stack_done
- ldo 128(sp),%r7
-
-/*
- * Switch to interrupt stack allocated by the interrupt manager (intr.c)
- */
- .import _CPU_Interrupt_stack_low,data
- ldil L%_CPU_Interrupt_stack_low,%r7
- ldw R%_CPU_Interrupt_stack_low(%r7),%r7
- ldo 128(%r7),%r7
-
-stack_done:
-/*
- * save our current stack pointer where the "old sp" is supposed to be
- */
- stw sp, -4(%r7)
-/*
- * and switch stacks (or advance old stack in nested case)
- */
- copy %r7, sp
-
-/*
- * increment the dispatch disable level counter.
- */
- addi 1,%r6,%r6
- stw %r6, 0(%r4)
-
-/*
- * load address of user handler
- * Note: No error checking is done, it is assumed that the
- * vector table contains a valid address or a stub
- * spurious handler.
- */
- .import _ISR_Vector_table,data
- ldil L%_ISR_Vector_table,%r8
- ldo R%_ISR_Vector_table(%r8),%r8
- ldw 0(%r8),%r8
- ldwx,s %r9(%r8),%r8
-
-/*
- * invoke user interrupt handler
- * Interrupts are currently disabled, as per RTEMS convention
- * The handler has the option of re-enabling interrupts
- * NOTE: can not use 'bl' since it uses "pc-relative" addressing
- * and we are using a hard coded address from a table
- * So... we fudge r2 ourselves (ala dynacall)
- * arg0 = vector number, arg1 = ptr to rtems_interrupt_frame
- */
- copy %r9, %r26
- .call ARGW0=GR, ARGW1=GR
- blr %r0, rp
- bv,n 0(%r8)
-
-post_user_interrupt_handler:
-
-/*
- * Back from user handler(s)
- * Disable external interrupts (since the interrupt handler could
- * have turned them on) and return to the interrupted task stack (assuming
- * (_ISR_Nest_level == 0)
- */
-
- rsm HPPA_PSW_I + HPPA_PSW_R, %r0
- ldw -4(sp), sp
-
-/*
- * r3 -- (most of) &_ISR_Nest_level
- * r5 -- value _ISR_Nest_level
- * r4 -- (most of) &_Thread_Dispatch_disable_level
- * r6 -- value _Thread_Dispatch_disable_level
- * r7 -- (most of) &_ISR_Signals_to_thread_executing
- * r8 -- value _ISR_Signals_to_thread_executing
- */
-
- .import _ISR_Nest_level,data
- ldil L%_ISR_Nest_level,%r3
- ldw R%_ISR_Nest_level(%r3),%r5
-
- .import _Thread_Dispatch_disable_level,data
- ldil L%_Thread_Dispatch_disable_level,%r4
- ldw R%_Thread_Dispatch_disable_level(%r4),%r6
-
- .import _ISR_Signals_to_thread_executing,data
- ldil L%_ISR_Signals_to_thread_executing,%r7
-
-/*
- * decrement isr nest level
- */
- addi -1, %r5, %r5
- stw %r5, R%_ISR_Nest_level(%r3)
-
-/*
- * decrement dispatch disable level counter and, if not 0, go on
- */
- addi -1,%r6,%r6
- comibf,= 0,%r6,isr_restore
- stw %r6, R%_Thread_Dispatch_disable_level(%r4)
-
-/*
- * check whether or not a context switch is necessary
- */
- .import _Context_Switch_necessary,data
- ldil L%_Context_Switch_necessary,%r8
- ldw R%_Context_Switch_necessary(%r8),%r8
- comibf,=,n 0,%r8,ISR_dispatch
-
-/*
- * check whether or not a context switch is necessary because an ISR
- * sent signals to the interrupted task
- */
- ldw R%_ISR_Signals_to_thread_executing(%r7),%r8
- comibt,=,n 0,%r8,isr_restore
-
-
-/*
- * OK, something happened while in ISR and we need to switch to a task
- * other than the one which was interrupted or the
- * ISR_Signals_to_thread_executing case
- * We also turn on interrupts, since the interrupted task had them
- * on (obviously :-) and Thread_Dispatch is happy to leave ints on.
- */
-
-ISR_dispatch:
- stw %r0, R%_ISR_Signals_to_thread_executing(%r7)
-
- ssm HPPA_PSW_I, %r0
-
- .import _Thread_Dispatch,code
- .call
- bl _Thread_Dispatch,%r2
- ldo 128(sp),sp
-
- ldo -128(sp),sp
-
-isr_restore:
-
-/*
- * enable interrupts during most of restore
- */
- ssm HPPA_PSW_I, %r0
-
-/*
- * Get a pointer to beginning of our stack frame
- */
- ldo -CPU_INTERRUPT_FRAME_SIZE(sp), %arg1
-
-/*
- * restore float
- */
- .call ARGW0=GR
- bl _CPU_Restore_float_context,%r2
- ldo FP_CONTEXT_OFFSET(%arg1), arg0
-
- copy %arg1, %arg0
-
-/*
- * ********** FALL THRU **********
- */
-
-/*
- * Jump here from bottom of Context_Switch
- * Also called directly by _CPU_Context_Restart_self via _Thread_Restart_self
- * restore interrupt state
- */
-
- .EXPORT _CPU_Context_restore
-_CPU_Context_restore:
-
-/*
- * restore integer state
- */
- ldw R1_OFFSET(arg0),%r1
- ldw R2_OFFSET(arg0),%r2
- ldw R3_OFFSET(arg0),%r3
- ldw R4_OFFSET(arg0),%r4
- ldw R5_OFFSET(arg0),%r5
- ldw R6_OFFSET(arg0),%r6
- ldw R7_OFFSET(arg0),%r7
- ldw R8_OFFSET(arg0),%r8
- ldw R9_OFFSET(arg0),%r9
- ldw R10_OFFSET(arg0),%r10
- ldw R11_OFFSET(arg0),%r11
- ldw R12_OFFSET(arg0),%r12
- ldw R13_OFFSET(arg0),%r13
- ldw R14_OFFSET(arg0),%r14
- ldw R15_OFFSET(arg0),%r15
- ldw R16_OFFSET(arg0),%r16
- ldw R17_OFFSET(arg0),%r17
- ldw R18_OFFSET(arg0),%r18
- ldw R19_OFFSET(arg0),%r19
- ldw R20_OFFSET(arg0),%r20
- ldw R21_OFFSET(arg0),%r21
- ldw R22_OFFSET(arg0),%r22
- ldw R23_OFFSET(arg0),%r23
- ldw R24_OFFSET(arg0),%r24
-/*
- * skipping r25; used as scratch register below
- * skipping r26 (arg0) until we are done with it
- */
- ldw R27_OFFSET(arg0),%r27
- ldw R28_OFFSET(arg0),%r28
- ldw R29_OFFSET(arg0),%r29
-/*
- * skipping r30 (sp) until we turn off interrupts
- */
- ldw R31_OFFSET(arg0),%r31
-
-/*
- * Turn off Q & R & I so we can write r30 and interrupt control registers
- */
- rsm HPPA_PSW_Q + HPPA_PSW_R + HPPA_PSW_I, %r0
-
-/*
- * now safe to restore r30
- */
- ldw R30_OFFSET(arg0),%r30
-
- ldw IPSW_OFFSET(arg0), %r25
- mtctl %r25, ipsw
-
- ldw SAR_OFFSET(arg0), %r25
- mtctl %r25, sar
-
- ldw PCOQFRONT_OFFSET(arg0), %r25
- mtctl %r25, pcoq
-
- ldw PCOQBACK_OFFSET(arg0), %r25
- mtctl %r25, pcoq
-
-/*
- * Load r25 with interrupts off
- */
- ldw R25_OFFSET(arg0),%r25
-/*
- * Must load r26 (arg0) last
- */
- ldw R26_OFFSET(arg0),%r26
-
-isr_exit:
- rfi
- .EXIT
- .PROCEND
-
-/*
- * This section is used to context switch floating point registers.
- * Ref: 6-35 of Architecture 1.1
- *
- * NOTE: since integer multiply uses the floating point unit,
- * we have to save/restore fp on every trap. We cannot
- * just try to keep track of fp usage.
- */
-
- .align 32
- .EXPORT _CPU_Save_float_context,ENTRY,PRIV_LEV=0
-_CPU_Save_float_context:
- .PROC
- .CALLINFO FRAME=0,NO_CALLS
- .ENTRY
- fstds,ma %fr0,8(%arg0)
- fstds,ma %fr1,8(%arg0)
- fstds,ma %fr2,8(%arg0)
- fstds,ma %fr3,8(%arg0)
- fstds,ma %fr4,8(%arg0)
- fstds,ma %fr5,8(%arg0)
- fstds,ma %fr6,8(%arg0)
- fstds,ma %fr7,8(%arg0)
- fstds,ma %fr8,8(%arg0)
- fstds,ma %fr9,8(%arg0)
- fstds,ma %fr10,8(%arg0)
- fstds,ma %fr11,8(%arg0)
- fstds,ma %fr12,8(%arg0)
- fstds,ma %fr13,8(%arg0)
- fstds,ma %fr14,8(%arg0)
- fstds,ma %fr15,8(%arg0)
- fstds,ma %fr16,8(%arg0)
- fstds,ma %fr17,8(%arg0)
- fstds,ma %fr18,8(%arg0)
- fstds,ma %fr19,8(%arg0)
- fstds,ma %fr20,8(%arg0)
- fstds,ma %fr21,8(%arg0)
- fstds,ma %fr22,8(%arg0)
- fstds,ma %fr23,8(%arg0)
- fstds,ma %fr24,8(%arg0)
- fstds,ma %fr25,8(%arg0)
- fstds,ma %fr26,8(%arg0)
- fstds,ma %fr27,8(%arg0)
- fstds,ma %fr28,8(%arg0)
- fstds,ma %fr29,8(%arg0)
- fstds,ma %fr30,8(%arg0)
- fstds %fr31,0(%arg0)
- bv 0(%r2)
- addi -(31*8), %arg0, %arg0 ; restore arg0 just for fun
- .EXIT
- .PROCEND
-
- .align 32
- .EXPORT _CPU_Restore_float_context,ENTRY,PRIV_LEV=0
-_CPU_Restore_float_context:
- .PROC
- .CALLINFO FRAME=0,NO_CALLS
- .ENTRY
- addi (31*8), %arg0, %arg0 ; point at last double
- fldds 0(%arg0),%fr31
- fldds,mb -8(%arg0),%fr30
- fldds,mb -8(%arg0),%fr29
- fldds,mb -8(%arg0),%fr28
- fldds,mb -8(%arg0),%fr27
- fldds,mb -8(%arg0),%fr26
- fldds,mb -8(%arg0),%fr25
- fldds,mb -8(%arg0),%fr24
- fldds,mb -8(%arg0),%fr23
- fldds,mb -8(%arg0),%fr22
- fldds,mb -8(%arg0),%fr21
- fldds,mb -8(%arg0),%fr20
- fldds,mb -8(%arg0),%fr19
- fldds,mb -8(%arg0),%fr18
- fldds,mb -8(%arg0),%fr17
- fldds,mb -8(%arg0),%fr16
- fldds,mb -8(%arg0),%fr15
- fldds,mb -8(%arg0),%fr14
- fldds,mb -8(%arg0),%fr13
- fldds,mb -8(%arg0),%fr12
- fldds,mb -8(%arg0),%fr11
- fldds,mb -8(%arg0),%fr10
- fldds,mb -8(%arg0),%fr9
- fldds,mb -8(%arg0),%fr8
- fldds,mb -8(%arg0),%fr7
- fldds,mb -8(%arg0),%fr6
- fldds,mb -8(%arg0),%fr5
- fldds,mb -8(%arg0),%fr4
- fldds,mb -8(%arg0),%fr3
- fldds,mb -8(%arg0),%fr2
- fldds,mb -8(%arg0),%fr1
- bv 0(%r2)
- fldds,mb -8(%arg0),%fr0
- .EXIT
- .PROCEND
-
-/*
- * These 2 small routines are unused right now.
- * Normally we just go thru _CPU_Save_float_context (and Restore)
- *
- * Here we just deref the ptr and jump up, letting _CPU_Save_float_context
- * do the return for us.
- */
-
- .EXPORT _CPU_Context_save_fp,ENTRY,PRIV_LEV=0
-_CPU_Context_save_fp:
- .PROC
- .CALLINFO FRAME=0,NO_CALLS
- .ENTRY
- bl _CPU_Save_float_context, %r0
- ldw 0(%arg0), %arg0
- .EXIT
- .PROCEND
-
- .EXPORT _CPU_Context_restore_fp,ENTRY,PRIV_LEV=0
-_CPU_Context_restore_fp:
- .PROC
- .CALLINFO FRAME=0,NO_CALLS
- .ENTRY
- bl _CPU_Restore_float_context, %r0
- ldw 0(%arg0), %arg0
- .EXIT
- .PROCEND
-
-
-/*
- * void _CPU_Context_switch( run_context, heir_context )
- *
- * This routine performs a normal non-FP context switch.
- */
-
- .align 32
- .EXPORT _CPU_Context_switch,ENTRY,PRIV_LEV=0,ARGW0=GR,ARGW1=GR
-_CPU_Context_switch:
- .PROC
- .CALLINFO FRAME=64
- .ENTRY
-
-/*
- * Save the integer context
- */
- stw %r1,R1_OFFSET(arg0)
- stw %r2,R2_OFFSET(arg0)
- stw %r3,R3_OFFSET(arg0)
- stw %r4,R4_OFFSET(arg0)
- stw %r5,R5_OFFSET(arg0)
- stw %r6,R6_OFFSET(arg0)
- stw %r7,R7_OFFSET(arg0)
- stw %r8,R8_OFFSET(arg0)
- stw %r9,R9_OFFSET(arg0)
- stw %r10,R10_OFFSET(arg0)
- stw %r11,R11_OFFSET(arg0)
- stw %r12,R12_OFFSET(arg0)
- stw %r13,R13_OFFSET(arg0)
- stw %r14,R14_OFFSET(arg0)
- stw %r15,R15_OFFSET(arg0)
- stw %r16,R16_OFFSET(arg0)
- stw %r17,R17_OFFSET(arg0)
- stw %r18,R18_OFFSET(arg0)
- stw %r19,R19_OFFSET(arg0)
- stw %r20,R20_OFFSET(arg0)
- stw %r21,R21_OFFSET(arg0)
- stw %r22,R22_OFFSET(arg0)
- stw %r23,R23_OFFSET(arg0)
- stw %r24,R24_OFFSET(arg0)
- stw %r25,R25_OFFSET(arg0)
- stw %r26,R26_OFFSET(arg0)
- stw %r27,R27_OFFSET(arg0)
- stw %r28,R28_OFFSET(arg0)
- stw %r29,R29_OFFSET(arg0)
- stw %r30,R30_OFFSET(arg0)
- stw %r31,R31_OFFSET(arg0)
-
-/*
- * fill in interrupt context section
- */
- stw %r2, PCOQFRONT_OFFSET(%arg0)
- ldo 4(%r2), %r2
- stw %r2, PCOQBACK_OFFSET(%arg0)
-
-/*
- * Generate a suitable IPSW by using the system default psw
- * with the current low bits added in.
- */
-
- ldil L%CPU_PSW_DEFAULT, %r2
- ldo R%CPU_PSW_DEFAULT(%r2), %r2
- ssm 0, %arg2
- dep %arg2, 31, 8, %r2
- stw %r2, IPSW_OFFSET(%arg0)
-
-/*
- * at this point, the running task context is completely saved
- * Now jump to the bottom of the interrupt handler to load the
- * heirs context
- */
-
- b _CPU_Context_restore
- copy %arg1, %arg0
-
- .EXIT
- .PROCEND
-
-
-/*
- * Find first bit
- * NOTE:
- * This is used (and written) only for the ready chain code and
- * priority bit maps.
- * Any other use constitutes fraud.
- * Returns first bit from the least significant side.
- * Eg: if input is 0x8001
- * output will indicate the '1' bit and return 0.
- * This is counter to HPPA bit numbering which calls this
- * bit 31. This way simplifies the macros _CPU_Priority_Mask
- * and _CPU_Priority_Bits_index.
- *
- * NOTE:
- * We just use 16 bit version
- * does not handle zero case
- *
- * Based on the UTAH Mach libc version of ffs.
- */
-
- .align 32
- .EXPORT hppa_rtems_ffs,ENTRY,PRIV_LEV=0,ARGW0=GR
-hppa_rtems_ffs:
- .PROC
- .CALLINFO FRAME=0,NO_CALLS
- .ENTRY
-
-#ifdef RETURN_ERROR_ON_ZERO
- comb,= %arg0,%r0,ffsdone ; If arg0 is 0
- ldi -1,%ret0 ; return -1
-#endif
-
-#if BITFIELD_SIZE == 32
- ldi 31,%ret0 ; Set return to high bit
- extru,= %arg0,31,16,%r0 ; If low 16 bits are non-zero
- addi,tr -16,%ret0,%ret0 ; subtract 16 from bitpos
- shd %r0,%arg0,16,%arg0 ; else shift right 16 bits
-#else
- ldi 15,%ret0 ; Set return to high bit
-#endif
- extru,= %arg0,31,8,%r0 ; If low 8 bits are non-zero
- addi,tr -8,%ret0,%ret0 ; subtract 8 from bitpos
- shd %r0,%arg0,8,%arg0 ; else shift right 8 bits
- extru,= %arg0,31,4,%r0 ; If low 4 bits are non-zero
- addi,tr -4,%ret0,%ret0 ; subtract 4 from bitpos
- shd %r0,%arg0,4,%arg0 ; else shift right 4 bits
- extru,= %arg0,31,2,%r0 ; If low 2 bits are non-zero
- addi,tr -2,%ret0,%ret0 ; subtract 2 from bitpos
- shd %r0,%arg0,2,%arg0 ; else shift right 2 bits
- extru,= %arg0,31,1,%r0 ; If low bit is non-zero
- addi -1,%ret0,%ret0 ; subtract 1 from bitpos
-ffsdone:
- bv,n 0(%r2)
- nop
- .EXIT
- .PROCEND
diff --git a/cpukit/score/cpu/hppa1.1/rtems/.cvsignore b/cpukit/score/cpu/hppa1.1/rtems/.cvsignore
deleted file mode 100644
index 282522db03..0000000000
--- a/cpukit/score/cpu/hppa1.1/rtems/.cvsignore
+++ /dev/null
@@ -1,2 +0,0 @@
-Makefile
-Makefile.in
diff --git a/cpukit/score/cpu/hppa1.1/rtems/score/.cvsignore b/cpukit/score/cpu/hppa1.1/rtems/score/.cvsignore
deleted file mode 100644
index 282522db03..0000000000
--- a/cpukit/score/cpu/hppa1.1/rtems/score/.cvsignore
+++ /dev/null
@@ -1,2 +0,0 @@
-Makefile
-Makefile.in
diff --git a/cpukit/score/cpu/hppa1.1/rtems/score/cpu.h b/cpukit/score/cpu/hppa1.1/rtems/score/cpu.h
deleted file mode 100644
index cce17efe6f..0000000000
--- a/cpukit/score/cpu/hppa1.1/rtems/score/cpu.h
+++ /dev/null
@@ -1,653 +0,0 @@
-/* cpu.h
- *
- * This include file contains information pertaining to the HP
- * PA-RISC processor (Level 1.1).
- *
- * COPYRIGHT (c) 1994 by Division Incorporated
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.com/license/LICENSE.
- *
- * Note:
- * This file is included by both C and assembler code ( -DASM )
- *
- * $Id$
- */
-
-#ifndef __CPU_h
-#define __CPU_h
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtems/score/hppa.h> /* pick up machine definitions */
-#ifndef ASM
-#include <rtems/score/types.h>
-#endif
-
-/* conditional compilation parameters */
-
-#define CPU_INLINE_ENABLE_DISPATCH FALSE
-#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
-
-/*
- * RTEMS manages an interrupt stack in software for the HPPA.
- */
-
-#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
-#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
-#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
-
-/*
- * Does the RTEMS invoke the user's ISR with the vector number and
- * a pointer to the saved interrupt frame (1) or just the vector
- * number (0)?
- */
-
-#define CPU_ISR_PASSES_FRAME_POINTER 0
-
-/*
- * HPPA has hardware FP, it is assumed to exist by GCC so all tasks
- * may implicitly use it (especially for integer multiplies). Because
- * the FP context is technically part of the basic integer context
- * on this CPU, we cannot use the deferred FP context switch algorithm.
- */
-
-#define CPU_HARDWARE_FP TRUE
-#define CPU_SOFTWARE_FP FALSE
-#define CPU_ALL_TASKS_ARE_FP TRUE
-#define CPU_IDLE_TASK_IS_FP FALSE
-#define CPU_USE_DEFERRED_FP_SWITCH FALSE
-
-#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
-#define CPU_STACK_GROWS_UP TRUE
-#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((__aligned__ (32)))
-
-/*
- * Define what is required to specify how the network to host conversion
- * routines are handled.
- */
-
-#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE
-#define CPU_BIG_ENDIAN TRUE
-#define CPU_LITTLE_ENDIAN FALSE
-
-/* constants */
-
-#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */
-#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */
-
-/*
- * PSW contstants
- */
-
-#define CPU_PSW_BASE (HPPA_PSW_C | HPPA_PSW_Q | HPPA_PSW_P | HPPA_PSW_D)
-#define CPU_PSW_INTERRUPTS_ON (CPU_PSW_BASE | HPPA_PSW_I)
-#define CPU_PSW_INTERRUPTS_OFF (CPU_PSW_BASE)
-
-#define CPU_PSW_DEFAULT CPU_PSW_BASE
-
-
-#ifndef ASM
-
-/*
- * Contexts
- *
- * This means we have the following context items:
- * 1. task level context stuff:: Context_Control
- * 2. floating point task stuff:: Context_Control_fp
- *
- * The PA-RISC is very fast so the expense of saving an extra register
- * or two is not of great concern at the present. So we are not making
- * a distinction between what is saved during a task switch and what is
- * saved at each interrupt. Plus saving the entire context should make
- * it easier to make gdb aware of RTEMS tasks.
- */
-
-typedef struct {
- unsigned32 flags; /* whatever */
- unsigned32 gr1; /* scratch -- caller saves */
- unsigned32 gr2; /* RP -- return pointer */
- unsigned32 gr3; /* scratch -- callee saves */
- unsigned32 gr4; /* scratch -- callee saves */
- unsigned32 gr5; /* scratch -- callee saves */
- unsigned32 gr6; /* scratch -- callee saves */
- unsigned32 gr7; /* scratch -- callee saves */
- unsigned32 gr8; /* scratch -- callee saves */
- unsigned32 gr9; /* scratch -- callee saves */
- unsigned32 gr10; /* scratch -- callee saves */
- unsigned32 gr11; /* scratch -- callee saves */
- unsigned32 gr12; /* scratch -- callee saves */
- unsigned32 gr13; /* scratch -- callee saves */
- unsigned32 gr14; /* scratch -- callee saves */
- unsigned32 gr15; /* scratch -- callee saves */
- unsigned32 gr16; /* scratch -- callee saves */
- unsigned32 gr17; /* scratch -- callee saves */
- unsigned32 gr18; /* scratch -- callee saves */
- unsigned32 gr19; /* scratch -- caller saves */
- unsigned32 gr20; /* scratch -- caller saves */
- unsigned32 gr21; /* scratch -- caller saves */
- unsigned32 gr22; /* scratch -- caller saves */
- unsigned32 gr23; /* argument 3 */
- unsigned32 gr24; /* argument 2 */
- unsigned32 gr25; /* argument 1 */
- unsigned32 gr26; /* argument 0 */
- unsigned32 gr27; /* DP -- global data pointer */
- unsigned32 gr28; /* return values -- caller saves */
- unsigned32 gr29; /* return values -- caller saves */
- unsigned32 sp; /* gr30 */
- unsigned32 gr31;
-
- /* Various control registers */
-
- unsigned32 sar; /* cr11 */
- unsigned32 ipsw; /* cr22; full 32 bits of psw */
- unsigned32 iir; /* cr19; interrupt instruction register */
- unsigned32 ior; /* cr21; interrupt offset register */
- unsigned32 isr; /* cr20; interrupt space register (not used) */
- unsigned32 pcoqfront; /* cr18; front que offset */
- unsigned32 pcoqback; /* cr18; back que offset */
- unsigned32 pcsqfront; /* cr17; front que space (not used) */
- unsigned32 pcsqback; /* cr17; back que space (not used) */
- unsigned32 itimer; /* cr16; itimer value */
-
-} Context_Control;
-
-
-/* Must be double word aligned.
- * This will be ok since our allocator returns 8 byte aligned chunks
- */
-
-typedef struct {
- double fr0; /* status */
- double fr1; /* exception information */
- double fr2; /* exception information */
- double fr3; /* exception information */
- double fr4; /* argument */
- double fr5; /* argument */
- double fr6; /* argument */
- double fr7; /* argument */
- double fr8; /* scratch -- caller saves */
- double fr9; /* scratch -- caller saves */
- double fr10; /* scratch -- caller saves */
- double fr11; /* scratch -- caller saves */
- double fr12; /* callee saves -- (PA-RISC 1.1 CPUs) */
- double fr13; /* callee saves -- (PA-RISC 1.1 CPUs) */
- double fr14; /* callee saves -- (PA-RISC 1.1 CPUs) */
- double fr15; /* callee saves -- (PA-RISC 1.1 CPUs) */
- double fr16; /* callee saves -- (PA-RISC 1.1 CPUs) */
- double fr17; /* callee saves -- (PA-RISC 1.1 CPUs) */
- double fr18; /* callee saves -- (PA-RISC 1.1 CPUs) */
- double fr19; /* callee saves -- (PA-RISC 1.1 CPUs) */
- double fr20; /* callee saves -- (PA-RISC 1.1 CPUs) */
- double fr21; /* callee saves -- (PA-RISC 1.1 CPUs) */
- double fr22; /* caller saves -- (PA-RISC 1.1 CPUs) */
- double fr23; /* caller saves -- (PA-RISC 1.1 CPUs) */
- double fr24; /* caller saves -- (PA-RISC 1.1 CPUs) */
- double fr25; /* caller saves -- (PA-RISC 1.1 CPUs) */
- double fr26; /* caller saves -- (PA-RISC 1.1 CPUs) */
- double fr27; /* caller saves -- (PA-RISC 1.1 CPUs) */
- double fr28; /* caller saves -- (PA-RISC 1.1 CPUs) */
- double fr29; /* caller saves -- (PA-RISC 1.1 CPUs) */
- double fr30; /* caller saves -- (PA-RISC 1.1 CPUs) */
- double fr31; /* caller saves -- (PA-RISC 1.1 CPUs) */
-} Context_Control_fp;
-
-/*
- * The following structure defines the set of information saved
- * on the current stack by RTEMS upon receipt of each interrupt.
- */
-
-typedef struct {
- Context_Control Integer;
- Context_Control_fp Floating_Point;
-} CPU_Interrupt_frame;
-
-/*
- * Our interrupt handlers take a 2nd argument:
- * a pointer to a CPU_Interrupt_frame
- * So we use our own prototype instead of rtems_isr_entry
- */
-
-typedef void ( *hppa_rtems_isr_entry )(
- unsigned32,
- CPU_Interrupt_frame *
- );
-
-/*
- * The following table contains the information required to configure
- * the HPPA specific parameters.
- */
-
-typedef struct {
- void (*pretasking_hook)( void );
- void (*predriver_hook)( void );
- void (*postdriver_hook)( void );
- void (*idle_task)( void );
- boolean do_zero_of_workspace;
- unsigned32 idle_task_stack_size;
- unsigned32 interrupt_stack_size;
- unsigned32 extra_mpci_receive_server_stack;
- void * (*stack_allocate_hook)( unsigned32 );
- void (*stack_free_hook)( void * );
- /* end of fields required on all CPUs */
-
- hppa_rtems_isr_entry spurious_handler;
-
- unsigned32 itimer_clicks_per_microsecond; /* for use by Clock driver */
-} rtems_cpu_table;
-
-/*
- * Macros to access required entires in the CPU Table are in
- * the file rtems/system.h.
- */
-
-/*
- * Macros to access HPPA specific additions to the CPU Table
- */
-
-#define rtems_cpu_configuration_get_spurious_handler() \
- (_CPU_Table.spurious_handler)
-
-#define rtems_cpu_configuration_get_itimer_clicks_per_microsecond() \
- (_CPU_Table.itimer_clicks_per_microsecond)
-
-/* variables */
-
-SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
-SCORE_EXTERN unsigned32 _CPU_Default_gr27;
-SCORE_EXTERN void *_CPU_Interrupt_stack_low;
-SCORE_EXTERN void *_CPU_Interrupt_stack_high;
-
-#endif /* ! ASM */
-
-/*
- * context sizes
- */
-
-#ifndef ASM
-#define CPU_CONTEXT_SIZE sizeof( Context_Control )
-#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
-#endif
-
-/*
- * size of a frame on the stack
- */
-
-#define CPU_FRAME_SIZE (16 * 4)
-
-/*
- * (Optional) # of bytes for libmisc/stackchk to check
- * If not specifed, then it defaults to something reasonable
- * for most architectures.
- */
-
-#define CPU_STACK_CHECK_SIZE (CPU_FRAME_SIZE * 2)
-
-/*
- * extra stack required by the MPCI receive server thread
- */
-
-#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
-
-/*
- * HPPA has 32 traps, then 32 external interrupts
- * Rtems (_ISR_Vector_Table) is aware ONLY of the first 32
- * The BSP is aware of the external interrupts and possibly more.
- *
- */
-
-#define CPU_INTERRUPT_NUMBER_OF_VECTORS (HPPA_INTERNAL_TRAPS)
-#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
-
-/*
- * This is defined if the port has a special way to report the ISR nesting
- * level. Most ports maintain the variable _ISR_Nest_level.
- */
-
-#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
-
-/*
- * Don't be chintzy here; we don't want to debug these problems
- * Some of the tests eat almost 4k.
- * Plus, the HPPA always allocates chunks of 64 bytes for stack
- * growth.
- */
-
-#define CPU_STACK_MINIMUM_SIZE (8 * 1024)
-
-/*
- * HPPA double's must be on 8 byte boundary
- */
-
-#define CPU_ALIGNMENT 8
-
-/*
- * just follow the basic HPPA alignment for the heap and partition
- */
-
-#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
-#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
-
-/*
- * HPPA stack is best when 64 byte aligned.
- */
-
-#define CPU_STACK_ALIGNMENT 64
-
-#ifndef ASM
-
-/* macros */
-
-/*
- * ISR handler macros
- *
- * These macros perform the following functions:
- * + initialize the RTEMS vector table
- * + disable all maskable CPU interrupts
- * + restore previous interrupt level (enable)
- * + temporarily restore interrupts (flash)
- * + set a particular level
- */
-
-/*
- * Support routine to initialize the RTEMS vector table after it is allocated.
- */
-
-#define _CPU_Initialize_vectors()
-
-/* Disable interrupts; returning previous psw bits in _isr_level */
-
-#define _CPU_ISR_Disable( _isr_level ) \
- do { \
- HPPA_ASM_RSM(HPPA_PSW_I, _isr_level); \
- if (_isr_level & HPPA_PSW_I) _isr_level = 0; \
- else _isr_level = 1; \
- } while(0)
-
-/* Enable interrupts to previous level from _CPU_ISR_Disable
- * does not change 'level'
- */
-
-#define _CPU_ISR_Enable( _isr_level ) \
- { \
- register int _ignore; \
- if (_isr_level == 0) HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \
- else HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \
- }
-
-/* restore, then disable interrupts; does not change level */
-#define _CPU_ISR_Flash( _isr_level ) \
- { \
- if (_isr_level == 0) \
- { \
- register int _ignore; \
- HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \
- HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \
- } \
- }
-
-/*
- * Interrupt task levels
- *
- * Future scheme proposal
- * level will be an index into a array.
- * Each entry of array will be the interrupt bits
- * enabled for that level. There will be 32 bits of external
- * interrupts (to be placed in EIEM) and some (optional) bsp
- * specific bits
- *
- * For pixel flow this *may* mean something like:
- * level 0: all interrupts enabled (external + rhino)
- * level 1: rhino disabled
- * level 2: all io interrupts disabled (timer still enabled)
- * level 7: *ALL* disabled (timer disabled)
- */
-
-/* set interrupts on or off; does not return new level */
-#define _CPU_ISR_Set_level( new_level ) \
- { \
- volatile int ignore; \
- if ( new_level ) HPPA_ASM_RSM(HPPA_PSW_I, ignore); \
- else HPPA_ASM_SSM(HPPA_PSW_I, ignore); \
- }
-
-/* return current level */
-unsigned32 _CPU_ISR_Get_level( void );
-
-/* end of ISR handler macros */
-
-/*
- * Context handler macros
- *
- * These macros perform the following functions:
- * + initialize a context area
- * + restart the current thread
- * + calculate the initial pointer into a FP context area
- * + initialize an FP context area
- *
- * HPPA port adds two macros which hide the "indirectness" of the
- * pointer passed the save/restore FP context assembly routines.
- */
-
-#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
- _new_level, _entry_point, _is_fp ) \
- do { \
- unsigned32 _stack; \
- \
- (_the_context)->flags = 0xfeedf00d; \
- (_the_context)->pcoqfront = (unsigned32)(_entry_point); \
- (_the_context)->pcoqback = (unsigned32)(_entry_point) + 4; \
- (_the_context)->pcsqfront = 0; \
- (_the_context)->pcsqback = 0; \
- if ( (_new_level) ) \
- (_the_context)->ipsw = CPU_PSW_INTERRUPTS_OFF; \
- else \
- (_the_context)->ipsw = CPU_PSW_INTERRUPTS_ON; \
- \
- _stack = ((unsigned32)(_stack_base) + (CPU_STACK_ALIGNMENT - 1)); \
- _stack &= ~(CPU_STACK_ALIGNMENT - 1); \
- if ((_stack - (unsigned32) (_stack_base)) < CPU_FRAME_SIZE) \
- _stack += CPU_FRAME_SIZE; \
- \
- (_the_context)->sp = (_stack); \
- (_the_context)->gr27 = _CPU_Default_gr27; \
- } while (0)
-
-#define _CPU_Context_Restart_self( _the_context ) \
- do { \
- _CPU_Context_restore( (_the_context) ); \
- } while (0)
-
-#define _CPU_Context_Fp_start( _base, _offset ) \
- ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
-
-#define _CPU_Context_Initialize_fp( _destination ) \
- do { \
- *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context;\
- } while(0)
-
-#define _CPU_Context_save_fp( _fp_context ) \
- _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context) )
-
-#define _CPU_Context_restore_fp( _fp_context ) \
- _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context) )
-
-/* end of Context handler macros */
-
-/*
- * Fatal Error manager macros
- *
- * These macros perform the following functions:
- * + disable interrupts and halt the CPU
- */
-
-void hppa_cpu_halt(unsigned32 the_error);
-#define _CPU_Fatal_halt( _error ) \
- hppa_cpu_halt(_error)
-
-/* end of Fatal Error manager macros */
-
-/*
- * Bitfield handler macros
- *
- * These macros perform the following functions:
- * + scan for the highest numbered (MSB) set in a 16 bit bitfield
- *
- * NOTE:
- *
- * The HPPA does not have a scan instruction. This functionality
- * is implemented in software.
- */
-
-#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
-#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
-
-int hppa_rtems_ffs(unsigned int value);
-#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
- _output = hppa_rtems_ffs(_value)
-
-/* end of Bitfield handler macros */
-
-/*
- * Priority handler macros
- *
- * These macros perform the following functions:
- * + return a mask with the bit for this major/minor portion of
- * of thread priority set.
- * + translate the bit number returned by "Bitfield_find_first_bit"
- * into an index into the thread ready chain bit maps
- *
- * Note: 255 is the lowest priority
- */
-
-#define _CPU_Priority_Mask( _bit_number ) \
- ( 1 << (_bit_number) )
-
-#define _CPU_Priority_bits_index( _priority ) \
- (_priority)
-
-/* end of Priority handler macros */
-
-/* functions */
-
-/*
- * _CPU_Initialize
- *
- * This routine performs CPU dependent initialization.
- */
-
-void _CPU_Initialize(
- rtems_cpu_table *cpu_table,
- void (*thread_dispatch)
-);
-
-/*
- * _CPU_ISR_install_raw_handler
- *
- * This routine installs a "raw" interrupt handler directly into the
- * processor's vector table.
- */
-
-void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-);
-
-/*
- * _CPU_ISR_install_vector
- *
- * This routine installs an interrupt vector.
- */
-
-void _CPU_ISR_install_vector(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-);
-
-/*
- * _CPU_Context_switch
- *
- * This routine switches from the run context to the heir context.
- */
-
-void _CPU_Context_switch(
- Context_Control *run,
- Context_Control *heir
-);
-
-/*
- * _CPU_Context_restore
- *
- * This routine is generally used only to restart self in an
- * efficient manner and avoid stack conflicts.
- */
-
-void _CPU_Context_restore(
- Context_Control *new_context
-);
-
-/*
- * _CPU_Save_float_context
- *
- * This routine saves the floating point context passed to it.
- *
- * NOTE: _CPU_Context_save_fp is implemented as a macro on the HPPA
- * which dereferences the pointer before calling this.
- */
-
-void _CPU_Save_float_context(
- Context_Control_fp *fp_context
-);
-
-/*
- * _CPU_Restore_float_context
- *
- * This routine restores the floating point context passed to it.
- *
- * NOTE: _CPU_Context_save_fp is implemented as a macro on the HPPA
- * which dereferences the pointer before calling this.
- */
-
-void _CPU_Restore_float_context(
- Context_Control_fp *fp_context
-);
-
-
-/*
- * The raw interrupt handler for external interrupts
- */
-
-extern void _Generic_ISR_Handler(
- void
-);
-
-
-/* The following routine swaps the endian format of an unsigned int.
- * It must be static so it can be referenced indirectly.
- */
-
-static inline unsigned int
-CPU_swap_u32(unsigned32 value)
-{
- unsigned32 swapped;
-
- HPPA_ASM_SWAPBYTES(value, swapped);
-
- return( swapped );
-}
-
-#define CPU_swap_u16( value ) \
- (((value&0xff) << 8) | ((value >> 8)&0xff))
-
-#endif /* ! ASM */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ! __CPU_h */
diff --git a/cpukit/score/cpu/hppa1.1/rtems/score/cpu_asm.h b/cpukit/score/cpu/hppa1.1/rtems/score/cpu_asm.h
deleted file mode 100644
index 951f80dcf0..0000000000
--- a/cpukit/score/cpu/hppa1.1/rtems/score/cpu_asm.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (c) 1990,1991 The University of Utah and
- * the Center for Software Science (CSS). All rights reserved.
- *
- * Permission to use, copy, modify and distribute this software is hereby
- * granted provided that (1) source code retains these copyright, permission,
- * and disclaimer notices, and (2) redistributions including binaries
- * reproduce the notices in supporting documentation, and (3) all advertising
- * materials mentioning features or use of this software display the following
- * acknowledgement: ``This product includes software developed by the Center
- * for Software Science at the University of Utah.''
- *
- * THE UNIVERSITY OF UTAH AND CSS ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
- * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSS DISCLAIM ANY LIABILITY OF
- * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- *
- * CSS requests users of this software to return to css-dist@cs.utah.edu any
- * improvements that they make and grant CSS redistribution rights.
- *
- * Utah $Hdr: asm.h 1.6 91/12/03$
- *
- * $Id$
- */
-
-/*
- * Hardware Space Registers
- */
-sr0 .reg %sr0
-sr1 .reg %sr1
-sr2 .reg %sr2
-sr3 .reg %sr3
-sr4 .reg %sr4
-sr5 .reg %sr5
-sr6 .reg %sr6
-sr7 .reg %sr7
-
-/*
- * Control register aliases
- */
-
-rctr .reg %cr0
-pidr1 .reg %cr8
-pidr2 .reg %cr9
-ccr .reg %cr10
-sar .reg %cr11
-pidr3 .reg %cr12
-pidr4 .reg %cr13
-iva .reg %cr14
-eiem .reg %cr15
-itmr .reg %cr16
-pcsq .reg %cr17
-pcoq .reg %cr18
-iir .reg %cr19
-isr .reg %cr20
-ior .reg %cr21
-ipsw .reg %cr22
-eirr .reg %cr23
-
-/*
- * Calling Convention
- */
-rp .reg %r2
-arg3 .reg %r23
-arg2 .reg %r24
-arg1 .reg %r25
-arg0 .reg %r26
-dp .reg %r27
-ret0 .reg %r28
-ret1 .reg %r29
-sl .reg %r29
-sp .reg %r30
-
-
diff --git a/cpukit/score/cpu/hppa1.1/rtems/score/hppa.h b/cpukit/score/cpu/hppa1.1/rtems/score/hppa.h
deleted file mode 100644
index 0eb9f977d7..0000000000
--- a/cpukit/score/cpu/hppa1.1/rtems/score/hppa.h
+++ /dev/null
@@ -1,727 +0,0 @@
-/*
- * Description:
- *
- * Definitions for HP PA Risc
- * ref: PA RISC 1.1 Architecture and Instruction Set Reference Manual
- *
- * COPYRIGHT (c) 1994 by Division Incorporated
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.com/license/LICENSE.
- *
- * Note:
- * This file is included by both C and assembler code ( -DASM )
- *
- * $Id$
- */
-
-#ifndef _INCLUDE_HPPA_H
-#define _INCLUDE_HPPA_H
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*
- * This section contains the information required to build
- * RTEMS for a particular member of the Hewlett Packard
- * PA-RISC family. It does this by setting variables to
- * indicate which implementation dependent features are
- * present in a particular member of the family.
- */
-
-/*
- * Hack to allow multlib effort to continue -- known to build.
- */
-
-#define CPU_MODEL_NAME "hppa 7xxx"
-#if 0
-#if defined(rtems_multilib)
-/*
- * Figure out all CPU Model Feature Flags based upon compiler
- * predefines.
- */
-
-#define CPU_MODEL_NAME "rtems_multilib"
-
-#elif defined(hppa7100)
-
-#define CPU_MODEL_NAME "hppa 7100"
-
-#elif defined(hppa7200)
-
-#define CPU_MODEL_NAME "hppa 7200"
-
-#else
-
-#error "Unsupported CPU Model"
-
-#endif
-#endif
-
-/*
- * Define the name of the CPU family.
- */
-
-#if !defined(CPU_NAME)
-#define CPU_NAME "HP PA-RISC 1.1"
-#endif
-
-/*
- * Processor Status Word (PSW) Masks
- */
-
-
-#define HPPA_PSW_Y 0x80000000 /* Data Debug Trap Disable */
-#define HPPA_PSW_Z 0x40000000 /* Instruction Debug Trap Disable */
-#define HPPA_PSW_r2 0x20000000 /* reserved */
-#define HPPA_PSW_r3 0x10000000 /* reserved */
-#define HPPA_PSW_r4 0x08000000 /* reserved */
-#define HPPA_PSW_E 0x04000000 /* Little Endian on Memory References */
-#define HPPA_PSW_S 0x02000000 /* Secure Interval Timer */
-#define HPPA_PSW_T 0x01000000 /* Taken Branch Trap Enable */
-#define HPPA_PSW_H 0x00800000 /* Higher-Privilege Transfer Trap Enable*/
-#define HPPA_PSW_L 0x00400000 /* Lower-Privilege Transfer Trap Enable */
-#define HPPA_PSW_N 0x00200000 /* PC Queue Front Instruction Nullified */
-#define HPPA_PSW_X 0x00100000 /* Data Memory Break Disable */
-#define HPPA_PSW_B 0x00080000 /* Taken Branch in Previous Cycle */
-#define HPPA_PSW_C 0x00040000 /* Code Address Translation Enable */
-#define HPPA_PSW_V 0x00020000 /* Divide Step Correction */
-#define HPPA_PSW_M 0x00010000 /* High-Priority Machine Check Disable */
-#define HPPA_PSW_CB 0x0000ff00 /* Carry/Borrow Bits */
-#define HPPA_PSW_r24 0x00000080 /* reserved */
-#define HPPA_PSW_G 0x00000040 /* Debug trap Enable */
-#define HPPA_PSW_F 0x00000020 /* Performance monitor interrupt unmask */
-#define HPPA_PSW_R 0x00000010 /* Recovery Counter Enable */
-#define HPPA_PSW_Q 0x00000008 /* Interruption State Collection Enable */
-#define HPPA_PSW_P 0x00000004 /* Protection ID Validation Enable */
-#define HPPA_PSW_D 0x00000002 /* Data Address Translation Enable */
-#define HPPA_PSW_I 0x00000001 /* External, Power Failure, */
- /* Low-Priority Machine Check */
- /* Interruption Enable */
-
-/*
- * HPPA traps and interrupts
- * basic layout. Note numbers do not denote priority
- *
- * 0-31 basic traps and interrupts defined by HPPA architecture
- * 0-31 32 external interrupts
- * 32-... bsp defined
- */
-
-#define HPPA_TRAP_NON_EXISTENT 0
-/* group 1 */
-#define HPPA_TRAP_HIGH_PRIORITY_MACHINE_CHECK 1
-/* group 2 */
-#define HPPA_TRAP_POWER_FAIL 2
-#define HPPA_TRAP_RECOVERY_COUNTER 3
-#define HPPA_TRAP_EXTERNAL_INTERRUPT 4
-#define HPPA_TRAP_LOW_PRIORITY_MACHINE_CHECK 5
-#define HPPA_TRAP_PERFORMANCE_MONITOR 29
-/* group 3 */
-#define HPPA_TRAP_INSTRUCTION_TLB_MISS 6
-#define HPPA_TRAP_INSTRUCTION_MEMORY_PROTECTION 7
-#define HPPA_TRAP_INSTRUCTION_DEBUG 30
-#define HPPA_TRAP_ILLEGAL_INSTRUCTION 8
-#define HPPA_TRAP_BREAK_INSTRUCTION 9
-#define HPPA_TRAP_PRIVILEGED_OPERATION 10
-#define HPPA_TRAP_PRIVILEGED_REGISTER 11
-#define HPPA_TRAP_OVERFLOW 12
-#define HPPA_TRAP_CONDITIONAL 13
-#define HPPA_TRAP_ASSIST_EXCEPTION 14
-#define HPPA_TRAP_DATA_TLB_MISS 15
-#define HPPA_TRAP_NON_ACCESS_INSTRUCTION_TLB_MISS 16
-#define HPPA_TRAP_NON_ACCESS_DATA_TLB_MISS 17
-#define HPPA_TRAP_DATA_MEMORY_ACCESS_RIGHTS 26
-#define HPPA_TRAP_DATA_MEMORY_PROTECTION_ID 27
-#define HPPA_TRAP_UNALIGNED_DATA_REFERENCE 28
-#define HPPA_TRAP_DATA_MEMORY_PROTECTION 18
-#define HPPA_TRAP_DATA_MEMORY_BREAK 19
-#define HPPA_TRAP_TLB_DIRTY_BIT 20
-#define HPPA_TRAP_PAGE_REFERENCE 21
-#define HPPA_TRAP_DATA_DEBUG 31
-#define HPPA_TRAP_ASSIST_EMULATION 22
-/* group 4 */
-#define HPPA_TRAP_HIGHER_PRIVILEGE_TRANSFER 23
-#define HPPA_TRAP_LOWER_PRIVILEGE_TRANSFER 24
-#define HPPA_TRAP_TAKEN_BRANCH 25
-
-#define HPPA_INTERNAL_TRAPS 32
-
-/* External Interrupts via interrupt 4 */
-
-#define HPPA_INTERRUPT_EXTERNAL_0 0
-#define HPPA_INTERRUPT_EXTERNAL_1 1
-#define HPPA_INTERRUPT_EXTERNAL_2 2
-#define HPPA_INTERRUPT_EXTERNAL_3 3
-#define HPPA_INTERRUPT_EXTERNAL_4 4
-#define HPPA_INTERRUPT_EXTERNAL_5 5
-#define HPPA_INTERRUPT_EXTERNAL_6 6
-#define HPPA_INTERRUPT_EXTERNAL_7 7
-#define HPPA_INTERRUPT_EXTERNAL_8 8
-#define HPPA_INTERRUPT_EXTERNAL_9 9
-#define HPPA_INTERRUPT_EXTERNAL_10 10
-#define HPPA_INTERRUPT_EXTERNAL_11 11
-#define HPPA_INTERRUPT_EXTERNAL_12 12
-#define HPPA_INTERRUPT_EXTERNAL_13 13
-#define HPPA_INTERRUPT_EXTERNAL_14 14
-#define HPPA_INTERRUPT_EXTERNAL_15 15
-#define HPPA_INTERRUPT_EXTERNAL_16 16
-#define HPPA_INTERRUPT_EXTERNAL_17 17
-#define HPPA_INTERRUPT_EXTERNAL_18 18
-#define HPPA_INTERRUPT_EXTERNAL_19 19
-#define HPPA_INTERRUPT_EXTERNAL_20 20
-#define HPPA_INTERRUPT_EXTERNAL_21 21
-#define HPPA_INTERRUPT_EXTERNAL_22 22
-#define HPPA_INTERRUPT_EXTERNAL_23 23
-#define HPPA_INTERRUPT_EXTERNAL_24 24
-#define HPPA_INTERRUPT_EXTERNAL_25 25
-#define HPPA_INTERRUPT_EXTERNAL_26 26
-#define HPPA_INTERRUPT_EXTERNAL_27 27
-#define HPPA_INTERRUPT_EXTERNAL_28 28
-#define HPPA_INTERRUPT_EXTERNAL_29 29
-#define HPPA_INTERRUPT_EXTERNAL_30 30
-#define HPPA_INTERRUPT_EXTERNAL_31 31
-
-#define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER HPPA_INTERRUPT_EXTERNAL_0
-#define HPPA_EXTERNAL_INTERRUPTS 32
-
-/* BSP defined interrupts begin here */
-
-#define HPPA_INTERRUPT_MAX 32
-
-/*
- * Cache characteristics
- */
-
-#define HPPA_CACHELINE_SIZE 32
-#define HPPA_CACHELINE_MASK (HPPA_CACHELINE_SIZE - 1)
-
-/*
- * page size characteristics
- */
-
-#define HPPA_PAGE_SIZE 4096
-#define HPPA_PAGE_MASK (0xfffff000)
-
-
-/*
- * TLB characteristics
- *
- * Flags and Access Control layout for using TLB protection insertion
- *
- * 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
- * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |?|?|T|D|B|type |PL1|Pl2|U| access id |?|
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- *
- */
-
-/*
- * Access rights (type + PL1 + PL2)
- */
-#define HPPA_PROT_R 0x00c00000 /* Read Only, no Write, no Execute */
-#define HPPA_PROT_RW 0x01c00000 /* Read & Write Only, no Execute */
-#define HPPA_PROT_RX 0x02c00000 /* Read & Execute Only, no Write */
-#define HPPA_PROT_RWX 0x03c00000 /* Read, Write, Execute */
-#define HPPA_PROT_X0 0x04c00000 /* Execute Only, Promote to Level 0 */
-#define HPPA_PROT_X1 0x05c00000 /* Execute Only, Promote to Level 1 */
-#define HPPA_PROT_X2 0x06c00000 /* Execute Only, Promote to Level 2 */
-#define HPPA_PROT_X3 0x07c00000 /* Execute Only, Promote to Level 3 */
-
-/*
- * Floating point status register definitions
- */
-
-#define HPPA_FPSTATUS_ENABLE_I 0x00000001 /* inexact operation */
-#define HPPA_FPSTATUS_ENABLE_U 0x00000002 /* underflow */
-#define HPPA_FPSTATUS_ENABLE_O 0x00000004 /* overflow */
-#define HPPA_FPSTATUS_ENABLE_Z 0x00000008 /* division by zero */
-#define HPPA_FPSTATUS_ENABLE_V 0x00000010 /* invalid operation */
-#define HPPA_FPSTATUS_D 0x00000020 /* denormalize as zero */
-#define HPPA_FPSTATUS_T 0x00000040 /* delayed trap */
-#define HPPA_FPSTATUS_RM_MASK 0x00000600 /* rounding mode */
-#define HPPA_FPSTATUS_RM_SHIFT 9
-#define HPPA_FPSTATUS_CQ_MASK 0x001FFC00 /* compare queue */
-#define HPPA_FPSTATUS_CQ_SHIFT 13
-#define HPPA_FPSTATUS_C 0x04000000 /* most recent ompare bit */
-#define HPPA_FPSTATUS_FLAG_I 0x08000000 /* inexact */
-#define HPPA_FPSTATUS_FLAG_U 0x10000000 /* underflow */
-#define HPPA_FPSTATUS_FLAG_O 0x20000000 /* overflow */
-#define HPPA_FPSTATUS_FLAG_Z 0x40000000 /* division by zero */
-#define HPPA_FPSTATUS_FLAG_V 0x80000000 /* invalid operation */
-
-
-/*
- * Inline macros for misc. interesting opcodes
- */
-
-/* generate a global label */
-#define HPPA_ASM_LABEL(label) \
- asm(".export " label ", ! .label " label);
-
-/* Return From Interrupt RFI */
-#define HPPA_ASM_RFI() asm volatile ("rfi")
-
-/* Set System Mask SSM i,t */
-#define HPPA_ASM_SSM(i,gr) asm volatile ("ssm %1, %0" \
- : "=r" (gr) \
- : "i" (i))
-/* Reset System Mask RSM i,t */
-#define HPPA_ASM_RSM(i,gr) asm volatile ("rsm %1, %0" \
- : "=r" (gr) \
- : "i" (i))
-/* Move To System Mask MTSM r */
-#define HPPA_ASM_MTSM(gr) asm volatile ("mtsm %0" \
- : : "r" (gr))
-
-/* Load Space Identifier LDSID (s,b),t */
-#define HPPA_ASM_LDSID(sr,grb,grt) asm volatile ("ldsid (%1,%2),%0" \
- : "=r" (grt) \
- : "i" (sr), \
- "r" (grb))
-
-/*
- * Gcc extended asm doesn't really allow for treatment of space registers
- * as "registers", so we have to use "i" format.
- * Unfortunately this means that the "=" constraint is not available.
- */
-
-/* Move To Space Register MTSP r,sr */
-#define HPPA_ASM_MTSP(gr,sr) asm volatile ("mtsp %1,%0" \
- : : "i" (sr), \
- "r" (gr))
-
-/* Move From Space Register MFSP sr,t */
-#define HPPA_ASM_MFSP(sr,gr) asm volatile ("mfsp %1,%0" \
- : "=r" (gr) \
- : "i" (sr))
-
-/* Move To Control register MTCTL r,t */
-#define HPPA_ASM_MTCTL(gr,cr) asm volatile ("mtctl %1,%0" \
- : : "i" (cr), \
- "r" (gr))
-
-/* Move From Control register MFCTL r,t */
-#define HPPA_ASM_MFCTL(cr,gr) asm volatile ("mfctl %1,%0" \
- : "=r" (gr) \
- : "i" (cr))
-
-/* Synchronize caches SYNC */
-#define HPPA_ASM_SYNC() asm volatile ("sync")
-
-/* Probe Read Access PROBER (s,b),r,t */
-#define HPPA_ASM_PROBER(sr,groff,gracc,grt) \
- asm volatile ("prober (%1,%2),%3,%0" \
- : "=r" (grt) \
- : "i" (sr), \
- "r" (groff), \
- "r" (gracc))
-
-/* Probe Read Access Immediate PROBERI (s,b),i,t*/
-#define HPPA_ASM_PROBERI(sr,groff,iacc,grt) \
- asm volatile ("proberi (%1,%2),%3,%0" \
- : "=r" (grt) \
- : "i" (sr), \
- "r" (groff), \
- "i" (iacc))
-
-/* Probe Write Access PROBEW (s,b),r,t */
-#define HPPA_ASM_PROBEW(sr,groff,gracc,grt) \
- asm volatile ("probew (%1,%2),%3,%0" \
- : "=r" (grt) \
- : "i" (sr), \
- "r" (groff), \
- "r" (gracc))
-
-/* Probe Write Access Immediate PROBEWI (s,b),i,t */
-#define HPPA_ASM_PROBEWI(sr,groff,iacc,grt) \
- asm volatile ("probewi (%1,%2),%3,%0" \
- : "=r" (grt) \
- : "i" (sr), \
- "r" (groff), \
- "i" (iacc))
-
-/* Load Physical Address LPA x(s,b),t */
-#define HPPA_ASM_LPA(sr,grb,grt) asm volatile ("lpa %%r0(%1,%2),%0" \
- : "=r" (grt) \
- : "i" (sr), \
- "r" (grb))
-
-/* Load Coherence Index LCI x(s,b),t */
-/* AKA: Load Hash Address LHA x(s,b),t */
-#define HPPA_ASM_LCI(grx,sr,grb,grt) asm volatile ("lha %1(%2,%3),%0" \
- : "=r" (grt) \
- : "r" (grx),\
- "i" (sr), \
- "r" (grb))
-#define HPPA_ASM_LHA(grx,sr,grb,grt) HPPA_ASM_LCI(grx,sr,grb,grt)
-
-/* Purge Data Tlb PDTLB x(s,b) */
-#define HPPA_ASM_PDTLB(grx,sr,grb) asm volatile ("pdtlb %0(%1,%2)" \
- : : "r" (grx), \
- "i" (sr), \
- "r" (grb))
-
-/* Purge Instruction Tlb PITLB x(s,b) */
-#define HPPA_ASM_PITLB(grx,sr,grb) asm volatile ("pitlb %0(%1,%2)" \
- : : "r" (grx), \
- "i" (sr), \
- "r" (grb))
-
-/* Purge Data Tlb Entry PDTLBE x(s,b) */
-#define HPPA_ASM_PDTLBE(grx,sr,grb) asm volatile ("pdtlbe %0(%1,%2)" \
- : : "r" (grx), \
- "i" (sr), \
- "r" (grb))
-
-/* Purge Instruction Tlb Entry PITLBE x(s,b) */
-#define HPPA_ASM_PITLBE(grx,sr,grb) asm volatile ("pitlbe %0(%1,%2)" \
- : : "r" (grx), \
- "i" (sr), \
- "r" (grb))
-
-
-/* Insert Data TLB Address IDTLBA r,(s,b) */
-#define HPPA_ASM_IDTLBA(gr,sr,grb) asm volatile ("idtlba %0,(%1,%2)" \
- : : "r" (gr), \
- "i" (sr), \
- "r" (grb))
-
-/* Insert Instruction TLB Address IITLBA r,(s,b) */
-#define HPPA_ASM_IITLBA(gr,sr,grb) asm volatile ("iitlba %0,(%1,%2)" \
- : : "r" (gr), \
- "i" (sr), \
- "r" (grb))
-
-/* Insert Data TLB Protection IDTLBP r,(s,b) */
-#define HPPA_ASM_IDTLBP(gr,sr,grb) asm volatile ("idtlbp %0,(%1,%2)" \
- : : "r" (gr), \
- "i" (sr), \
- "r" (grb))
-
-/* Insert Instruction TLB Protection IITLBP r,(s,b) */
-#define HPPA_ASM_IITLBP(gr,sr,grb) asm volatile ("iitlbp %0,(%1,%2)" \
- : : "r" (gr), \
- "i" (sr), \
- "r" (grb))
-
-/* Purge Data Cache PDC x(s,b) */
-#define HPPA_ASM_PDC(grx,sr,grb) asm volatile ("pdc %0(%1,%2)" \
- : : "r" (grx), \
- "i" (sr), \
- "r" (grb))
-
-/* Flush Data Cache FDC x(s,b) */
-#define HPPA_ASM_FDC(grx,sr,grb) asm volatile ("fdc %0(%1,%2)" \
- : : "r" (grx), \
- "i" (sr), \
- "r" (grb))
-
-/* Flush Instruction Cache FDC x(s,b) */
-#define HPPA_ASM_FIC(grx,sr,grb) asm volatile ("fic %0(%1,%2)" \
- : : "r" (grx), \
- "i" (sr), \
- "r" (grb))
-
-/* Flush Data Cache Entry FDCE x(s,b) */
-#define HPPA_ASM_FDCE(grx,sr,grb) asm volatile ("fdce %0(%1,%2)" \
- : : "r" (grx), \
- "i" (sr), \
- "r" (grb))
-
-/* Flush Instruction Cache Entry FICE x(s,b) */
-#define HPPA_ASM_FICE(grx,sr,grb) asm volatile ("fice %0(%1,%2)" \
- : : "r" (grx), \
- "i" (sr), \
- "r" (grb))
-
-/* Break BREAK i5,i13 */
-#define HPPA_ASM_BREAK(i5,i13) asm volatile ("break %0,%1" \
- : : "i" (i5), \
- "i" (i13))
-
-/* Load and Clear Word Short LDCWS d(s,b),t */
-#define HPPA_ASM_LDCWS(i,sr,grb,grt) asm volatile ("ldcws %1(%2,%3),%0" \
- : "=r" (grt) \
- : "i" (i), \
- "i" (sr), \
- "r" (grb))
-
-/* Load and Clear Word Indexed LDCWX x(s,b),t */
-#define HPPA_ASM_LDCWX(grx,sr,grb,grt) asm volatile ("ldcwx %1(%2,%3),%0" \
- : "=r" (grt) \
- : "r" (grx), \
- "i" (sr), \
- "r" (grb))
-
-/* Load Word Absolute Short LDWAS d(b),t */
-/* NOTE: "short" here means "short displacement" */
-#define HPPA_ASM_LDWAS(disp,grbase,gr) asm volatile("ldwas %1(%2),%0" \
- : "=r" (gr) \
- : "i" (disp), \
- "r" (grbase))
-
-/* Store Word Absolute Short STWAS r,d(b) */
-/* NOTE: "short" here means "short displacement" */
-#define HPPA_ASM_STWAS(gr,disp,grbase) asm volatile("stwas %0,%1(%2)" \
- : : "r" (gr), \
- "i" (disp), \
- "r" (grbase))
-
-/*
- * Swap bytes
- * REFERENCE: PA72000 TRM -- Appendix C
- */
-#define HPPA_ASM_SWAPBYTES(value, swapped) asm volatile( \
- " shd %1,%1,16,%0 \n\
- dep %0,15,8,%0 \n\
- shd %1,%0,8,%0" \
- : "=r" (swapped) \
- : "r" (value) \
- )
-
-
-/* 72000 Diagnose instructions follow
- * These macros assume gas knows about these instructions.
- * gas2.2.u1 did not.
- * I added them to my copy and installed it locally.
- *
- * There are *very* special requirements for these guys
- * ref: TRM 6.1.3 Programming Constraints
- *
- * The macros below handle the following rules
- *
- * Except for WIT, WDT, WDD, WIDO, WIDE, all DIAGNOSE must be doubled.
- * Must never be nullified (hence the leading nop)
- * NOP must preced every RDD,RDT,WDD,WDT,RDTLB
- * Instruction preceeding GR_SHDW must not set any of the GR's saved
- *
- * The macros do *NOT* deal with the following problems
- * doubled DIAGNOSE instructions must not straddle a page boundary
- * if code translation enabled. (since 2nd could trap on ITLB)
- * If you care about DHIT and DPE bits of DR0, then
- * No store instruction in the 2 insn window before RDD
- */
-
-
-/* Move To CPU/DIAG register MTCPU r,t */
-#define HPPA_ASM_MTCPU(gr,dr) asm volatile (" nop \n" \
- " mtcpu %1,%0 \n" \
- " mtcpu %1,%0" \
- : : "i" (dr), \
- "r" (gr))
-
-/* Move From CPU/DIAG register MFCPU r,t */
-#define HPPA_ASM_MFCPU(dr,gr) asm volatile (" nop \n" \
- " mfcpu %1,%0\n" \
- " mfcpu %1,%0" \
- : "=r" (gr) \
- : "i" (dr))
-
-/* Transfer of Control Enable TOC_EN */
-#define HPPA_ASM_TOC_EN() asm volatile (" tocen \n" \
- " tocen")
-
-/* Transfer of Control Disable TOC_DIS */
-#define HPPA_ASM_TOC_DIS() asm volatile (" tocdis \n" \
- " tocdis")
-
-/* Shadow Registers to General Register SHDW_GR */
-#define HPPA_ASM_SHDW_GR() asm volatile (" shdwgr \n" \
- " shdwgr" \
- ::: "r1" "r8" "r9" "r16" \
- "r17" "r24" "r25")
-
-/* General Registers to Shadow Register GR_SHDW */
-#define HPPA_ASM_GR_SHDW() asm volatile (" nop \n" \
- " grshdw \n" \
- " grshdw")
-
-/*
- * Definitions of special registers for use by the above macros.
- */
-
-/* Hardware Space Registers */
-#define HPPA_SR0 0
-#define HPPA_SR1 1
-#define HPPA_SR2 2
-#define HPPA_SR3 3
-#define HPPA_SR4 4
-#define HPPA_SR5 5
-#define HPPA_SR6 6
-#define HPPA_SR7 7
-
-/* Hardware Control Registers */
-#define HPPA_CR0 0
-#define HPPA_RCTR 0 /* Recovery Counter Register */
-
-#define HPPA_CR8 8 /* Protection ID 1 */
-#define HPPA_PIDR1 8
-
-#define HPPA_CR9 9 /* Protection ID 2 */
-#define HPPA_PIDR2 9
-
-#define HPPA_CR10 10
-#define HPPA_CCR 10 /* Coprocessor Confiquration Register */
-
-#define HPPA_CR11 11
-#define HPPA_SAR 11 /* Shift Amount Register */
-
-#define HPPA_CR12 12
-#define HPPA_PIDR3 12 /* Protection ID 3 */
-
-#define HPPA_CR13 13
-#define HPPA_PIDR4 13 /* Protection ID 4 */
-
-#define HPPA_CR14 14
-#define HPPA_IVA 14 /* Interrupt Vector Address */
-
-#define HPPA_CR15 15
-#define HPPA_EIEM 15 /* External Interrupt Enable Mask */
-
-#define HPPA_CR16 16
-#define HPPA_ITMR 16 /* Interval Timer */
-
-#define HPPA_CR17 17
-#define HPPA_PCSQ 17 /* Program Counter Space queue */
-
-#define HPPA_CR18 18
-#define HPPA_PCOQ 18 /* Program Counter Offset queue */
-
-#define HPPA_CR19 19
-#define HPPA_IIR 19 /* Interruption Instruction Register */
-
-#define HPPA_CR20 20
-#define HPPA_ISR 20 /* Interruption Space Register */
-
-#define HPPA_CR21 21
-#define HPPA_IOR 21 /* Interruption Offset Register */
-
-#define HPPA_CR22 22
-#define HPPA_IPSW 22 /* Interrpution Processor Status Word */
-
-#define HPPA_CR23 23
-#define HPPA_EIRR 23 /* External Interrupt Request */
-
-#define HPPA_CR24 24
-#define HPPA_PPDA 24 /* Physcial Page Directory Address */
-#define HPPA_TR0 24 /* Temporary register 0 */
-
-#define HPPA_CR25 25
-#define HPPA_HTA 25 /* Hash Table Address */
-#define HPPA_TR1 25 /* Temporary register 1 */
-
-#define HPPA_CR26 26
-#define HPPA_TR2 26 /* Temporary register 2 */
-
-#define HPPA_CR27 27
-#define HPPA_TR3 27 /* Temporary register 3 */
-
-#define HPPA_CR28 28
-#define HPPA_TR4 28 /* Temporary register 4 */
-
-#define HPPA_CR29 29
-#define HPPA_TR5 29 /* Temporary register 5 */
-
-#define HPPA_CR30 30
-#define HPPA_TR6 30 /* Temporary register 6 */
-
-#define HPPA_CR31 31
-#define HPPA_CPUID 31 /* MP identifier */
-
-/*
- * Diagnose registers
- */
-
-#define HPPA_DR0 0
-#define HPPA_DR1 1
-#define HPPA_DR8 8
-#define HPPA_DR24 24
-#define HPPA_DR25 25
-
-/*
- * Tear apart a break instruction to find its type.
- */
-#define HPPA_BREAK5(x) ((x) & 0x1F)
-#define HPPA_BREAK13(x) (((x) >> 13) & 0x1FFF)
-
-/* assemble a break instruction */
-#define HPPA_BREAK(i5,i13) (((i5) & 0x1F) | (((i13) & 0x1FFF) << 13))
-
-
-/*
- * this won't work in ASM or non-GNU compilers
- */
-
-#if !defined(ASM) && defined(__GNUC__)
-
-/*
- * static inline utility functions to get at control registers
- */
-
-#define EMIT_GET_CONTROL(name, reg) \
-static __inline__ unsigned int \
-get_ ## name (void) \
-{ \
- unsigned int value; \
- HPPA_ASM_MFCTL(reg, value); \
- return value; \
-}
-
-#define EMIT_SET_CONTROL(name, reg) \
-static __inline__ void \
-set_ ## name (unsigned int new_value) \
-{ \
- HPPA_ASM_MTCTL(new_value, reg); \
-}
-
-#define EMIT_CONTROLS(name, reg) \
- EMIT_GET_CONTROL(name, reg) \
- EMIT_SET_CONTROL(name, reg)
-
-EMIT_CONTROLS(recovery, HPPA_RCTR); /* CR0 */
-EMIT_CONTROLS(pid1, HPPA_PIDR1); /* CR8 */
-EMIT_CONTROLS(pid2, HPPA_PIDR2); /* CR9 */
-EMIT_CONTROLS(ccr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
-EMIT_CONTROLS(scr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
-EMIT_CONTROLS(sar, HPPA_SAR); /* CR11 */
-EMIT_CONTROLS(pid3, HPPA_PIDR3); /* CR12 */
-EMIT_CONTROLS(pid4, HPPA_PIDR4); /* CR13 */
-EMIT_CONTROLS(iva, HPPA_IVA); /* CR14 */
-EMIT_CONTROLS(eiem, HPPA_EIEM); /* CR15 */
-EMIT_CONTROLS(itimer, HPPA_ITMR); /* CR16 */
-EMIT_CONTROLS(pcsq, HPPA_PCSQ); /* CR17 */
-EMIT_CONTROLS(pcoq, HPPA_PCOQ); /* CR18 */
-EMIT_CONTROLS(iir, HPPA_IIR); /* CR19 */
-EMIT_CONTROLS(isr, HPPA_ISR); /* CR20 */
-EMIT_CONTROLS(ior, HPPA_IOR); /* CR21 */
-EMIT_CONTROLS(ipsw, HPPA_IPSW); /* CR22 */
-EMIT_CONTROLS(eirr, HPPA_EIRR); /* CR23 */
-EMIT_CONTROLS(tr0, HPPA_TR0); /* CR24 */
-EMIT_CONTROLS(tr1, HPPA_TR1); /* CR25 */
-EMIT_CONTROLS(tr2, HPPA_TR2); /* CR26 */
-EMIT_CONTROLS(tr3, HPPA_TR3); /* CR27 */
-EMIT_CONTROLS(tr4, HPPA_TR4); /* CR28 */
-EMIT_CONTROLS(tr5, HPPA_TR5); /* CR29 */
-EMIT_CONTROLS(tr6, HPPA_TR6); /* CR30 */
-EMIT_CONTROLS(tr7, HPPA_CR31); /* CR31 */
-
-#endif /* ASM and GNU */
-
-/*
- * If and How to invoke the debugger (a ROM debugger generally)
- */
-#define CPU_INVOKE_DEBUGGER \
- do { \
- HPPA_ASM_BREAK(1,1); \
- } while (0)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ! _INCLUDE_HPPA_H */
-
diff --git a/cpukit/score/cpu/hppa1.1/rtems/score/types.h b/cpukit/score/cpu/hppa1.1/rtems/score/types.h
deleted file mode 100644
index 512323819b..0000000000
--- a/cpukit/score/cpu/hppa1.1/rtems/score/types.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* hppatypes.h
- *
- * This include file contains type definitions pertaining to the Hewlett
- * Packard PA-RISC processor family.
- *
- * $Id$
- */
-
-#ifndef _INCLUDE_HPPATYPES_H
-#define _INCLUDE_HPPATYPES_H
-
-#ifndef ASM
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * This section defines the basic types for this processor.
- */
-
-typedef unsigned char unsigned8; /* 8-bit unsigned integer */
-typedef unsigned short unsigned16; /* 16-bit unsigned integer */
-typedef unsigned int unsigned32; /* 32-bit unsigned integer */
-typedef unsigned long long unsigned64; /* 64-bit unsigned integer */
-
-typedef unsigned16 Priority_Bit_map_control;
-
-typedef signed char signed8; /* 8-bit signed integer */
-typedef signed short signed16; /* 16-bit signed integer */
-typedef signed int signed32; /* 32-bit signed integer */
-typedef signed long long signed64; /* 64 bit signed integer */
-
-typedef unsigned32 boolean; /* Boolean value */
-
-typedef float single_precision; /* single precision float */
-typedef double double_precision; /* double precision float */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* !ASM */
-
-#endif /* _INCLUDE_HPPATYPES_H */
-/* end of include file */
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