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| author | Jan Sommer <jan.sommer@dlr.de> | 2020-08-20 09:18:06 +0200 |
|---|---|---|
| committer | Chris Johns <chrisj@rtems.org> | 2020-08-22 17:30:12 +1000 |
| commit | 61ccb9c05dcd695114541960aa6bfc1315f30514 (patch) | |
| tree | 9cbe58acf9fce52abf72f934fbf5455105c6df3a | |
| parent | confdefs: Fix cyclic dependency (diff) | |
| download | rtems-61ccb9c05dcd695114541960aa6bfc1315f30514.tar.bz2 | |
bsp/xilinx-zynq: Flush TX-Buffer before initializing uart5.1
Closes #4055
Closes #4056
| -rw-r--r-- | bsps/arm/shared/serial/zynq-uart-polled.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/bsps/arm/shared/serial/zynq-uart-polled.c b/bsps/arm/shared/serial/zynq-uart-polled.c index 4e0ca46aca..e6f478ee07 100644 --- a/bsps/arm/shared/serial/zynq-uart-polled.c +++ b/bsps/arm/shared/serial/zynq-uart-polled.c @@ -122,6 +122,8 @@ void zynq_uart_initialize(rtems_termios_device_context *base) uint32_t brgr = 0x3e; uint32_t bauddiv = 0x6; + zynq_uart_reset_tx_flush(ctx); + zynq_cal_baud_rate(ZYNQ_UART_DEFAULT_BAUD, &brgr, &bauddiv, regs->mode); regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN); |