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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2004-11-23 15:31:19 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2004-11-23 15:31:19 +0000 |
| commit | 21b54fc117a0b48c64a182d6ad858b1106662a89 (patch) | |
| tree | bfafa335a991671b86f1e07587a8e96c03be67e2 | |
| parent | Add PR617 as fixed by conversion to new exceptions. (diff) | |
| download | rtems-21b54fc117a0b48c64a182d6ad858b1106662a89.tar.bz2 | |
2004-11-23 Richard Campbell <richard.campbell@oarcorp.com>
* powerpc/mpc6xx/mmu/mmuAsm.S: Enable L1 instruction cache only for
mpc8240 and mpc8245.
| -rw-r--r-- | c/src/lib/libcpu/ChangeLog | 5 | ||||
| -rw-r--r-- | c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S | 14 |
2 files changed, 18 insertions, 1 deletions
diff --git a/c/src/lib/libcpu/ChangeLog b/c/src/lib/libcpu/ChangeLog index 8eef55fe8e..a16fa0a7c5 100644 --- a/c/src/lib/libcpu/ChangeLog +++ b/c/src/lib/libcpu/ChangeLog @@ -1,3 +1,8 @@ +2004-11-23 Richard Campbell <richard.campbell@oarcorp.com> + + * powerpc/mpc6xx/mmu/mmuAsm.S: Enable L1 instruction cache only for + mpc8240 and mpc8245. + 2003-09-04 Joel Sherrill <joel@OARcorp.com> * shared/include/cache.h, shared/src/cache_aligned_malloc.c, diff --git a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S index 01a055ca24..dff4499abc 100644 --- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S +++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S @@ -18,6 +18,7 @@ #include <asm.h> #include <rtems/score/cpu.h> #include <libcpu/io.h> +#include <bspopts.h> /* Unfortunately, the CPU types defined in cpu.h are * an 'enum' type and hence not available :-( @@ -137,7 +138,18 @@ L1_caches_enables: beq 4f /* not needed for 601 */ mfspr r11,HID0 andi. r0,r11,HID0_DCE - ori r11,r11,HID0_ICE|HID0_DCE +#if defined(mpc8240) || defined(mpc8245) + /* + * Data cache is broken for mpc8240 and mpc8245, + * enable instruction cache only. + */ + ori r11,r11,HID0_ICE +#else + /* + * Enable both instruction and data caches + */ + ori r11,r11,HID0_ICE|HID0_DCE +#endif ori r8,r11,HID0_ICFI bne 3f /* don't invalidate the D-cache */ ori r8,r8,HID0_DCI /* unless it wasn't enabled */ |