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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2004-02-26 17:23:58 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2004-02-26 17:23:58 +0000 |
commit | 1a17efbd2d6087396180cb087a964f2bcb7f8168 (patch) | |
tree | 5a0c97be7c042719acfe4cf610fdf52f8dbb8d66 | |
parent | 2004-02-26 Thomas Rauscher <trauscher@loytec.com. (diff) | |
download | rtems-1a17efbd2d6087396180cb087a964f2bcb7f8168.tar.bz2 |
2004-02-26 Andreas Karlsson <andreas.karlsson@space.se>
* cpu_asm.S: Close window while restoring interrupted task state which
resulted in CWP corruption.
-rw-r--r-- | cpukit/score/cpu/sparc/ChangeLog | 5 | ||||
-rw-r--r-- | cpukit/score/cpu/sparc/cpu_asm.S | 11 |
2 files changed, 16 insertions, 0 deletions
diff --git a/cpukit/score/cpu/sparc/ChangeLog b/cpukit/score/cpu/sparc/ChangeLog index 2ddc22ca1e..280a5d1944 100644 --- a/cpukit/score/cpu/sparc/ChangeLog +++ b/cpukit/score/cpu/sparc/ChangeLog @@ -1,3 +1,8 @@ +2004-02-26 Andreas Karlsson <andreas.karlsson@space.se> + + * cpu_asm.S: Close window while restoring interrupted task state which + resulted in CWP corruption. + 2003-09-04 Joel Sherrill <joel@OARcorp.com> * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/sparc.h, diff --git a/cpukit/score/cpu/sparc/cpu_asm.S b/cpukit/score/cpu/sparc/cpu_asm.S index ec0dce2bb9..357e3dcbd4 100644 --- a/cpukit/score/cpu/sparc/cpu_asm.S +++ b/cpukit/score/cpu/sparc/cpu_asm.S @@ -684,6 +684,17 @@ SYM(_ISR_Dispatch): call SYM(_Thread_Dispatch), 0 nop + /* + * We invoked _Thread_Dispatch in a state similar to the interrupted + * task. In order to safely be able to tinker with the register + * windows and get the task back to its pre-interrupt state, + * we need to disable interrupts disabled so we can safely tinker + * with the register windowing. In particular, the CWP in the PSR + * is fragile during this period. (See PR578.) + */ + mov 2,%g1 ! syscall (disable interrupts) + ta 0 ! syscall (disable interrupts) + /* * The CWP in place at this point may be different from * that which was in effect at the beginning of the ISR if we |