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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-05-31 15:27:40 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-05-31 15:27:40 +0000 |
| commit | 322c894c08fcda35ac6942e2adf4441fc6f25ae1 (patch) | |
| tree | 79432c48c34930d4f77f30ea68fe4a70d14bfc09 | |
| parent | Patch rtems-rc-4.5.0-25.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de> (diff) | |
| download | rtems-322c894c08fcda35ac6942e2adf4441fc6f25ae1.tar.bz2 | |
Patch to:
1. Fixes a typo in the code conditionalized by GEN68360_WITH_SRAM
2. Mods the code to add support for an additional bank of SRAM (needed more RAM
to run the web server!)
From <vac4050@cae597.rsc.raytheon.com> reviewed by Eric Norum <eric@cls.usask.ca>.
| -rw-r--r-- | c/src/lib/libbsp/m68k/gen68360/startup/init68360.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c b/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c index 8a68524766..522a8fdd5d 100644 --- a/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c +++ b/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c @@ -347,6 +347,7 @@ void _Init68360 (void) * But uses SRAM instead of DRAM * * CS0* - 512kx8 flash memory * * CS1* - 512kx32 static RAM * + * CS2* - 512kx32 static RAM * *************************************************** */ @@ -418,12 +419,16 @@ void _Init68360 (void) /* * Step 12: Set up main memory * 512Kx32 SRAM on CS1* + * 512Kx32 SRAM on CS2* * 0 wait states */ - ramSize = 1 * 1024 * 1024; + ramSize = 4 * 1024 * 1024; m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V; m360.memc[1].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB | M360_MEMC_OR_32BIT; + m360.memc[2].br = ((unsigned long)&_RamBase + 0x200000) | M360_MEMC_BR_V; + m360.memc[2].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB | + M360_MEMC_OR_32BIT; /* * Step 13: Copy the exception vector table to system RAM */ @@ -463,12 +468,6 @@ void _Init68360 (void) * SIM60 interrupt sources higher priority than CPM */ m360.mcr = 0x4C7F; - * No show cycles - * User/supervisor access - * Bus clear interrupt service level 7 - * SIM60 interrupt sources higher priority than CPM - */ - m360.mcr = 0x4C7F; #else /* |