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authorJoel Sherrill <joel.sherrill@OARcorp.com>2011-04-20 20:28:07 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2011-04-20 20:28:07 +0000
commitf7761ea0643758c1ffa86852ab420d5fb0d05619 (patch)
treef3417b30f31c1b54b1ca6888398bb76511f7faa5
parent2011-04-20 Rohan Kangralkar <rkangral@ece.neu.edu> (diff)
downloadrtems-f7761ea0643758c1ffa86852ab420d5fb0d05619.tar.bz2
Fix formatting.
-rw-r--r--c/src/lib/libbsp/bfin/TLL6527M/ChangeLog16
-rw-r--r--c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog7
-rw-r--r--c/src/lib/libcpu/bfin/ChangeLog14
-rw-r--r--cpukit/score/cpu/bfin/ChangeLog7
4 files changed, 8 insertions, 36 deletions
diff --git a/c/src/lib/libbsp/bfin/TLL6527M/ChangeLog b/c/src/lib/libbsp/bfin/TLL6527M/ChangeLog
index 4d6c325e41..261c253a37 100644
--- a/c/src/lib/libbsp/bfin/TLL6527M/ChangeLog
+++ b/c/src/lib/libbsp/bfin/TLL6527M/ChangeLog
@@ -1,11 +1,11 @@
2011-04-20 Rohan Kangralkar <rkangral@ece.neu.edu>
- PR 1781/bsps
- * ChangeLog, Makefile.am, README, bsp_specs, configure.ac,
- preinstall.am, times, console/console.c, include/bsp.h,
- include/cplb.h, include/tm27.h, make/custom/TLL6527M.cfg,
- startup/bspstart.c, startup/linkcmds: New files.
- Initial port for the TLL6527Mboard that contains blackfin 52X
- range of processors. Used eZKit533 as a reference for building
- the port.
+ PR 1781/bsps
+ * ChangeLog, Makefile.am, README, bsp_specs, configure.ac,
+ preinstall.am, times, console/console.c, include/bsp.h,
+ include/cplb.h, include/tm27.h, make/custom/TLL6527M.cfg,
+ startup/bspstart.c, startup/linkcmds: New files.
+ Initial port for the TLL6527Mboard that contains blackfin 52X
+ range of processors. Used eZKit533 as a reference for building
+ the port.
diff --git a/c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog b/c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog
index ecfe0e4adf..88b9a7d85d 100644
--- a/c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog
+++ b/c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog
@@ -5,13 +5,6 @@
now. So the array containing the registeration changes. The
change is due to change in the libcup uart function.
-2011-04-20 Rohan Kangralkar <rkangral@ece.neu.edu>
-------------------------------------------------------------------------
-r36 | rkangral | 2011-03-15 16:59:39 -0400 (Tue, 15 Mar 2011) | 1 line
- * console/console-io.c: The UART RX and TX are different ISR now. So the
- array containing the registeration changes. The change is due to change
- in the libcup uart function.
-
2011-02-02 Ralf Corsépius <ralf.corsepius@rtems.org>
* configure.ac: Require autoconf-2.68, automake-1.11.1.
diff --git a/c/src/lib/libcpu/bfin/ChangeLog b/c/src/lib/libcpu/bfin/ChangeLog
index 1859b4a8b9..2c515d1364 100644
--- a/c/src/lib/libcpu/bfin/ChangeLog
+++ b/c/src/lib/libcpu/bfin/ChangeLog
@@ -12,20 +12,6 @@
type of interrupt is identified by the central ISR dispatcher
bf52x/interrupt or interrupt/. This simplifies the UART ISR.
-2011-04-40 Rohan Kangralkar <rkangral@ece.neu.edu>
-
- * bf52x/include: Added additional MMR.
- * bf52x/interrupt: The BF52X processors have a different System interrupt
- controller than present in the 53X range of processors. The 52X have 8
- interrupt assignment registers. The implementation uses tables to increase
- predictability.
- * serial/uart.?: Added DMA based and interrupt based transfer support. The
- old uart code used a single ISR for TX and RX and tried to identify and
- multiplex inside the ISR. In the new code the type of interrupt is
- identified by the central ISR dispatcher bf52x/interrupt or interrupt/.
- This simplifies the UART ISR.
-
-
2011-02-02 Ralf Corsépius <ralf.corsepius@rtems.org>
* configure.ac: Require autoconf-2.68, automake-1.11.1.
diff --git a/cpukit/score/cpu/bfin/ChangeLog b/cpukit/score/cpu/bfin/ChangeLog
index 581cf8c72d..be1693a061 100644
--- a/cpukit/score/cpu/bfin/ChangeLog
+++ b/cpukit/score/cpu/bfin/ChangeLog
@@ -6,13 +6,6 @@
Processor Hardware Reference from Analog Devices. Mentioned
Chapters refer to this Documentation.
-2011-04-20 Rohan Kangralkar <rkangral@ece.neu.edu>
-
- * bfin/rtems/bf52x.h: This file defines basic MMR for the Blackfin 52x CPU.
- The MMR have been taken from the ADSP-BF52x Blackfin Processor
- Hardware Reference from Analog Devices. Mentioned Chapters
- refer to this Documentation.
-
2010-04-20 Allan Hessenflow <allanh@kallisti.com>
* cpu_asm.S: L0-L3 were part of the interrupt context, but as