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#  $Id$

This is the RTEMS entry in the Crossgcc FAQ at @uref{}.
As of 8/19/99, it has been submitted twice and the FAQ not updated.

RTEMS is a freely available, royalty free real-time executive with
multiprocessor capabilities.  RTEMS' design provides performance and
capabilities are comparable to those of the best commercial executives.
The directive execution times and other critical performance measures such
as interrupt latency are best of class. RTEMS was developed by On-Line
Applications Research Corporation (OAR) under contract to the U.S. Army
Missile Command. 

RTEMS includes support for multiple APIs.  Currently RTEMS supports a
POSIX threads API, and an RTEID based API which is similar to pSOS+. 
RTEMS includes a number of advanced real-time features including optional
rate monotonic scheduling support, binary semapahores with priority
inheritance, and watchdog timer functions. 

RTEMS includes a port of the FreeBSD TCP/IP stack that has high
performance on very modest hardware.  A remote debug server is supported
on some targets that allows debugging across the network. 

RTEMS provides a rich run-time environment with a reentrant C library,
POSIX 1003.1b support, and file system support.  It also includes optional
debug aids like stack overflow and heap integrity checking. 

RTEMS is built using GNU autoconf and can be built on any host supporting
the GNU tools including GNU/Linux, FreeBSD, NetBSD, Solaris, and MS-Windows
to name but a few.  The current RTEMS release supports the following CPU

  Motorola m680x0, m683xx, and ColdFire
  Motorola and IBM PowerPC (4xx, 5xx, 6xx, 7xx, 8xx, and 84xx) 
  Hitachi SH-1, SH-2, SH-4
  Hitachi H8
  Intel i386, i486, Pentium, and i960
  Texas Instruments C3x/C4x
  OpenCores OR32

There are over 35 Board Support Packages included with RTEMS including
BSPs for a standard PC as well as the SPARC, MIPS, PowerPC simulators
included with gdb.  There are numerous BSPs for CPUs targetting the
embedded market such as the Motorola m683xx, ppc4xx, and mpc8xx series
which support the on-CPU peripherals.